EECS 298-11: CAD Seminar Friday, May 2, 1997, 11am ^^^^^^ ^^^^ Cory Hall--Hogan Room Architectural Retiming: A Technique for Pipelining Latency-Constrained Circuits Soha Hassoun University of Washington Seattle, WA In designing high-performance digital synchronous circuits substantial effort is exerted to achieve target performance. A common performance bottleneck consists of a path that cannot be further pipelined due to latency constraints. Current approaches are ad hoc and are based on the experience and skill of the designer. This talk presents a new technique for pipelining latency-constrained circuits. The technique improves performance by adding a pipeline register and a negative register along the latency-constrained path. The pipeline register increases the number of clock cycles available along the path, thus decreasing the clock cycle, while the negative register counteracts the latency of the pipeline register, thus preserving the latency and functionality of the circuit. Two realizations of the negative register are possible: precomputation, and prediction. The optimization technique is called architectural retiming, as it both changes the timing of the circuit and modifies its structure to preserve latency and functionality. I will begin this talk by describing how latency constraints arise in practice. I will then explain how to model latency constraints and how to find the latency-constraint path that limits the circuit's performance. Next, I will present the architectural retiming technique and the implementations of the negative register. I will demonstrate how architectural retiming can generate architectural transformations such as look-ahead and bypassing. I will conclude by showing the results of applying architectural retiming to some example circuits and describing future work. This work was done with Prof. Carl Ebeling in the CSE department at the University of Washington.