EECS 298-11: CAD Seminar
Wednesday, February 12, 1997, 5pm
Cory Hall--Hogan Room

         Power Estimation and Optimization in IC Design

                      Massoud Pedram
                University of Southern California

Low power has emerged as a principal theme in today's electronic
industry.  The need for low power has caused a major paradigm shift
(in certain market segments) in which power dissipation is as
important as circuit speed and area. This talk presents some of the
techniques developed by my research group at USC to address the
challenge to reduce power while preserving the circuit speed.
 
I will first present our recent results in power estimation at gate
level and register transfer level, including probabilistic,
statistical and information theoretic techniques. Special emphasis
will be given to capacitance estimation, input data modeling, and
effects of circuit structure and delay equations on
accuracy/efficiency trade-off.  I will then describe a sample of our
design techniques for power optimization at the behavioral, logic and
layout levels of abstraction. Emphasis will be given to techniques
that consider both circuit speed and power dissipation factors and
their trade-off in the design process.  The efficacy of various power
estimation and minimization techniques will be illustrated with
benchmark circuits and with examples and data taken from industry.