EECS 298-11: CAD Seminar
Wednesday, April 2 , 1997, 5pm
Cory Hall--Hogan Room


Improvements in Technology Independent Optimization of Logic Circuits

                           Hamid Savoj
                       Cadence Design Inc.

This talk describes improvements to technology independent transformation 
applied to a logic circuit to make them more efficient. In particular, 
it discusses how to control BDD operatrions and memory usage during don't 
care computation and node simplification so that the whole algorithm 
is not aborted when a BDD oper ation fails, and how to reduce memory usage 
in fast_extract.

An optimization flow is presented that is not script based. A circuit 
is optimized iteratively as long as the size of that circuit decreases. 
The optimization algorithms work automatically on every circuit we have 
tried so far and no intervention is required. Our results are as good 
as the best reported in on small circuits and much better on 
larger circuits where full_simplify could not be applied before. The 
new full_simplify takes much less CPU time than the one in SIS.