Low power design: challenges and perspectives


Power dissipation is a growing concern for both high-performance and low-cost portable systems. In this talk I will first overview the efforts that have been made to tackle power dissipation at various level of abstraction. I will focus on computer-aided techniques for the estimation and minimization of power in digital circuits, which have been subject of my research effort during my PhD at Stanford University.

In the second part of the talk, I will concentrate on power estimation and optimization at the system level (chip level and above). In this area, relatively few results have been presented by the academic community, while several industry-lead efforts are under way. I will present the basics of a mathematical model for power-managed systems and discuss its application to the problem of finding optimal power management policies. Moreover, I will analyze some of the implications (and opportunities) of power management on current and future hardware designs.

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