Compiling, Synthesis, and Simulation of V++
The V++ Hardware Design Language is a novel language designed with the following goals:
V++ was designed with the lessons learned from software programming languages. In particular, V++ was designed with a universal communication device, the stack, in mind. In this talk, we address the problem of compiling, synthesis, and simulation V++ programs.
- To be a mechanism for capturing the design, not modeling the design. Hardware description languages like VHDL or Verilog were principally targeted at design modeling; the design itself was represented elsewhere. Contrast this with a high-level language program. In the programmer's mind, there is no distinction between the program and the implementation. The program is the implementation. Similarly, a V++ program should be the designer's view of the part to be implemented.
- To present a single, well-defined, tool-neutral semantics to the user. Verilog, of course, dreadfully abused its user community by having its semantics defined by the operations of the Verilog simulator. VHDL did somewhat better: the standard body simultaneously defined the simulator and the language, so that at least there was an accurate reference manual. However, the semantics were still defined in terms of simulation, which led to inconsistencies between the behavior of part's code and the behavior of that part. A better approach defines the semantics independent of an interpretation tool: indeed, in terms of the underlying implementation medium, digital hardware at some level of abstraction.
- To solve the problem of compositionality - the behavior of two well-defined V++ parts, when composed, is well-defined.
- To make the execution flow explicit - this will enable us to utilize well-developed optimization techniques on large designs.