High-Level Power Estimation and Modeling
The power dissipation of large integrated circuits is now a critical concern. Modern microprocessors are hot, and their average power consumption can exceed 50 Watts, and has even reached 300 Watts in one case. Through the contributions of many research groups, both in academia and in industry, a low-power design methodology has been evolving which aims to control and manage the power dissipation. By the time the design has been specified down to the circuit or gate level, it may be too late or too expensive to go back and fix high power problems. Thus, in order to enable early power estimation and to avoid costly redesign steps, power estimation is required at a high level of abstraction. In this talk, I will describe on-going work at Illinois on high-level power estimation and modeling. I will cover two approaches to the problem: bottom-up and top-down. In the bottom-up approach, it is assumed that the low-level (gate or transistor) structure of the circuit is known, and the aim is to develop a higher-level power macromodel that allows the user to estimate the power from knowledge of the circuit input/output signal statistics. In the top-down approach, we estimate the power given only a functional RT level description (Boolean equations and memory elements), and no gate-level structure. This is done by estimating the average internal switching activity and the total capacitance of an optimal implementation of the circuit.
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