On Retiming and Resynthesis Transformations


Retiming and resynthesis transformations can be used for optimizing the area, power, and delay of sequential circuits. Even though this technique has been known for more than a decade, its exact optimization capability has not been formally established. In this talk I will show that retiming and resynthesis can exactly implement {\em 1-step equivalent\/} state transition graph transformations. This result is the strongest to date. I will also show how the notions of retiming and resynthesis can be moderately extended to achieve more powerful state transition graph transformations. Time permitting, I will briefly touch upon the verification issue related with these transformations. In particular, I will show that equivalence checking after performing repeated retiming and synthesis on certain class of circuits reduces to a combinational verification problem. The applicability of this technique is demonstrated by applying it to a set of benchmarks and industrial designs.

Relevant Papers

R. Ranjan, V. Singhal, F. Somenzi, R. Brayton "Using Combinational Verification for Sequential Circuits" , IWLS98.

R. Ranjan, V. Singhal, F. Somenzi, R. Brayton. "On the Optimization Power of Retiming and Resynthesis Transformations" , Technical report UCB/ERL M98/26.


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