Solutions to the interconnect design and analysis bottleneck
AbstractRapid device scaling and the subsequent increase in switching speeds have highlighted the limitations of on-chip metal interconnects to carry fast signals while insuring low loss and high integrity. Effects such as signal crosstalk, bounce, and delay have become dominant due to reduction in metal width, ptich and width to height aspect ratio. In order to manage these effects, new circuit engineering methods, computer-aided design and verification techniques, and process technology variations will have to overcome the inherent limitations of metal in dielectric. An overview of the "interconnect problem" is presented and a discussion of possible solution diretions is given. Inductance usage, Logic/timing orthogonality, transmission line design, metal planes, full wave modeling and model reduction, hierarchical interconnects, computational area limitation, asynchronous design, and other techniques will be discussed.
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E. Chiprout, "Interconnect and substrate modeling and analysis: an overview" , proc. Bipolar/BiCMOS circuits and technology meeting (BCTM), Minneapolis MN, Sept. 1997.
R. Achar, M. Nakhla and E. Chiprout "Block CFH -- a model reduction technique for multiport distributed interconnect networks", European Conference on circuit theory and design", Aug. 1997, Budapest Hungary.
J. Phillips, E. Chiprout and D. Ling "A full-wave electromagnetic modeling code with model-order reduction and multilevel matrix decomposition", Progress in Electromagetics Research Symposium (PIERS), July, 1997, Cambridge, MA
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A. Ruehli and E. Chiprout, "The importance of retardation in PEEC models for electrical interconnect and package (EIP) applications", proc. IEEE 4th topical meeting on Electrical Performance of Electronic Packaging, Oct, 1995.
J. Phillips, E. Chiprout, D. Ling "Efficient full-wave electromagnetic analysis via model order reduction of fast integral transforms", Design Automation Conference, Las Vagas, June, 1996.
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