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CAD Challenges for High Performance and
Low Power Processor Designs at Motorola.
Abstract
As designs are entering feature sizes of 0.18 microns with 1 GHz or more
performance targets, new problems are emerging for CAD tools. In this
talk we will give an overview of the ongoing research at the
Advanced Tools Group at Motorola. We will also present the newly
emerging CAD challenges at the circuit and interconnect level for high
performance and low power processor designs. We will address some of these problems,
specifically the problems of leakage current estimation and optimization using
a Dual-Vt process, and power grid integrity analysis. For each area, we will briefly
present the industrial context of the problem, our current research and
solutions, and the future work and issues that need to be addressed by academic
and industrial research.
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