Timing Closure Methodology


Despite the increasing performance that modern processes offer, timing is becoming more and more the dominant design objective in modern integrated circuits. Unfortunately, timing is mostly dominated by parasitics, which can only be determined when the design is finished. To break out of this apparent paradox, we propose a solution where the methodology controls the parasitics and sizes throughout the design flow to conform to timing requirements. Such a methodology heavily relies on sizing capabilities. We will also discuss some of the practical complications and limitations to sizing.
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