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Simulation
Simulation, although not ``formal verification'', is an alternate
method for design verification.
After the command build_partition_mdds is invoked, the network can
also be simulated.
In VIS we provide internal simulation of the BLIF-MV description
generated by VL2MV, via the simulate command.
Thus, VIS encompasses both formal verification and simulation capabilities.
simulate can generate random input patterns or accept user-specified
input patterns.
Any level of the specified hierarchy may be simulated;
the user may traverse the hierarchy to reach the relevant level via the
cd command and simulate only that part.
The init_verify command must be called to set up the appropriate internal
data structures before simulation.
Roderick Bloem
2001-05-21
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