Workspaces
----
apbd
asves
asvpapers
bear
blast
caltrop
cases
concurrency
cosi
dif
diva
dopcenter
dopresence
dopsysadmin
eecsx44
elab
embedded
embeddedadmin
giotto
hyinfo
m2t2
mescal
metropolis
mica
mobies
msgadmin
murieh
mvsis
nephest
ransom
recons
robosysadmin
savg
sec
seminar
smartnets
video
webmaster
Note:
JavaScript is disabled
, see the
Site Map
for navigation links
 
Non-determinism in Verilog
Non-determinism in Verilog
$ND construct
Creates a non-deterministic signal source
Should only be used in an assign statement
Should be used only to create non-deterministic constants
/* definition of a wire variable */
wire rand_choice;
/* non-determinism */
assign rand_choice = $ND(0,1);
Previous slide
Back to the first slide
View Graphic Version