Monthly R&D Status Report Date: March 15, 1996 Title: "SYSTEM-LEVEL DESIGN METHODOLOGY FOR EMBEDDED SIGNAL PROCESSORS" Contract Number: F33615-93-C-1317 Principal Investigator: Edward A. Lee Organization: University of California at Berkeley 1. Tasks Performed The major activities in this reporting period were the releas of Ptolemy 0.6 alpha, our Industrial Liaison Program conference, and a number of other public interactions. 2. Significant Accomplishments 2.1. Scheduling Praveen Murthy is in the process of implementing the optimizing loop schedulers that he and Shuvra Bhattacharyya have developed and published in several papers. He is also implementing a random graph generation mechanism for testing schedulers. 2.2. Control and Signal Processing Bilung Lee continues to make great progress on the hierarchical FSM domain integration in Ptolemy. He has integrated the visual FSM editor (written by Wan-Teh Chang) into the Ptolemy GUI so that a user can seamlessly traverse a hierarchical design that combines FSMs with dataflow block diagrams. He has developed some simplified applications that illustrate hierarchical states and concurrency (using dataflow as the communication model). Wan-Teh Chang has prototyped C++ and Tcl interfaces to the dynamic higher-order functions mechanism, in which we dynamically switch in a replacement block. This can be used to implement hierarchical state machines (with no cross-hierarchy state transitions), and dynamically evaluated higher-order functions. For example, we can implement conditionals (like if-then-else) within a dataflow actor as a HOF by using the C++ interface. 2.3. VHDL Synthesis Mike Williamson has installed a suite of demos for his new VHDL domain, including a beamforming implementation. These demos work with the Synopsys VHDL simulator. Our license to the Model Technology simulator has expired, so we do not know whether it will work with that. 2.4. Distributed Signal Processing Patrick Warner's NOW (network of workstations) target in the CGC domain (code generation in C) is operational, and will be included in the 0.6 release. It is built on top of an active message abstraction. However, its performance is disappointing. The communication and rsh costs are excessive. We are evaluating strategies to improve performance. 2.5. Design Flow Management John Reekie developed String and File datatypes in the Ptolemy kernel to support design flow management. We are now implementing design flow management under the dataflow domains using these datatypes, rather than in a separate domain, as we had previously planned. 2.6. Technical Improvements to Ptolemy We have removed several older and more esoteric domains from Ptolemy with the objective of getting the size of what we need to support down. Mike Williamson significantly improved the speed of code generation in Ptolemy by using Quantify to track down the bottlenecks. Jose' Pino made some other technical improvements to the code generation infrastructure. Brian Evans fixed a large number of subtle and not so subtle bugs and plugged a few remaining memory leaks. He also modified the code generation process for DSP assembly code to report the amount of program and data memory used. Ptolemy now compiles under HPPA CC. Ptolemy almost compiles under SunSoft CC4.0, only one file does not build. The CGC TclTk Target now uses Makefile_C target, which results in a much more configurable build. We have determined that using shared tcl/tk libraries to build CGC TclTk targets can result in a compile that is 15 times faster than using non-shared tcl/tk libraries. Tom Parks (now at Lincoln Labs) ported the Process Network domain to Solaris 2.5. Unfortunately, the Posix thread support in Solaris 2.5 is still not up to the full standard, so we are still using a third party implementation of the thread library. 2.7. Technical Improvements to Tycho Christopher Hylands verified that we can get itcl2.0 to work under tcl7.5b1/tk4.1b1. More work is needed here, but using tk4.1 would mean that we can use the photo widget and experiment with tcl style incremental linking. Ptolemy can also be built with tcl7.5b3/tk4.1 without itcl We have reorganized the directory structure for Tycho to plan for growth. 2.8. Release Information We had a one-week code freeze, from March 1 to March 7, after which we split the Ptolemy tree and separated the 0.6 version from the development tree. The 0.6 alpha version of Ptolemy was released on March 15. Participants include engineers from Hewlett Packard, Cirrus Logic, Precedence (now part of Mentor), Silicon and Software Systems, Comsat, Fiat, Thomson, Synopsys, Boston University, the Technical Universities in Dresden, Hagen, and Ilmenau, Germany, and Seoul National University in Korea. 3. Meetings and Interactions. Brian Evans visited Boston University between February 17th and 22nd to assist with preparation of the BU/MIT RASSP software for synchronized release with Ptolemy 0.6. The Integrated Signal Processing and Understanding of Signals (IPUS) domain in Ptolemy is an encapsulation of the ICP tool, both developed by the Knowledge-Based Signal Processing Laboratory at Boston University. IPUS/ICP is an architecture for knowledge-based control of signal processing systems. Applications include radar clutter analysis (CAT), signal reprocessing, and planning. Demonstrations are installed in the default initial palette. At BU, the primary developer of the software implementation of IPUS and ICP has been Joseph Winograd (winograd@bu.edu). Alain Girault, a postdoctoral researcher in the Ptolemy group, gave a talk at Berkeley on March 1, 1996, entitled "Distributing Reactive Systems." We held our annual Industrial Liaison Program conference on March 13 and 14 in Berkeley. The Ptolemy project was involved in a special session on the Design of Embedded Systems, organized jointly with Prof. Alberto Sangiovanni-Vincentelli. We also conducted demos of Ptolemy and Tycho on both days. Prof. Lee gave a 4 hour introduction to DSP at the DSPx conference in San Jose, California on March 11, 1996. Fritz Heinrichmeyer of the FernUniversitaet in Hagen, Germany, and his colleagues have created a code generation domain for the Texas Instruments C50 DSP processor. It is still in fairly preliminary form. We are considering working on and supporting it if they will allow us free access to their source code. 5. Publications The following papers have been submitted: [1] T. Parks and E. A. Lee, "A Policy for Bounded Scheduling of Process Networks," submitted to PACT '96. [2] S. A. Edwards, W.-T. Chang, A. Girault, and E. A. Lee, "Heterogeneous Design of Systems using Control and Dataflow," submitted to PACT '96.