Jeffery Bier, Sundararajan Sriram and Edward A. Lee
IEEE International Symposium on Circuits and Systems, pp. 2622-2625, Vol. 4, May 1-3, 1990.
ABSTRACT
A class of high-performance, low-cost architectures that rely on the ability to predict, at compile time, the order in which shared resources (such as shared memories) will be accessed by the processors is discussed. If this ordering can be predicted at compile time and enforced at run time, then no hardware or software overhead is required for resolving contention for shared resources, and extremely efficient interprocessor communication is possible. Further, no overhead (such as semaphore management) is required for synchronization of the programs running on the component processors. The hardware required to enforce the ordered access of the shared resources is very simple. The result is a very lean multiprocessor architecture with very efficient access to shared resources. A specific example using Motorola DSP96002 processors and a shared memory is described in detail.
