An Implementation of Behavioral Verilog Simulator in Ptolemy

by Pai Chou

MS Report, University of Washington, Department of Computer Science & Engineering, November, 1992.



Modeling and simulation of digital hardware at the behavioral level enable designers to experiment with a system without specifying implementation details. Verilog is a language that supports modeling and simulation at different levels of abstraction. However, all components in the same design must conform to a certain timing model, which may not be natural for all components. Ptolemy is a simulation environment for systems with heterogeneous timing models. This report describes the incorporation of the behavioral Verilog simulator into Ptolemy by a compiler, which expresses the simulation semantics