Mapping Multiple Independent Synchronous Dataflow Graphs
The fundamental building block of a multiprocessor target is a single processor target. In our example, shown in figure 1, we have an Ariel S-56X card installed in a workstation. An S56X target describes the DSP card by specifying the memory resources available on the card and how to download the code into the program memory of the DSP. The S56X target generates assembly code and allocates target-specific resources such as private memory. A CGC target describes the resources of the workstation and generates code in the C programming language. This target is more general than the S56X target; the code it generates can run on most general-purpose computers.
A multiprocessor target is built by including other targets as children in a hierarchy. These children can be any type of target, from a simple single processor to a complex heterogeneous multiprocessor. The parent multiprocessor target specifies the shared resources and inter-processor communication mechanisms of the children in the form of send/receive and peek/poke actors. In the example shown in figure 1, the CGC-S56X target is built from single-processor CGC and S56X targets. A homogeneous multi-DSP target is described in [8].