Variables

Variables can be used to simplify makefiles. A variable definition looks like this:

FOO = bar baz

Backslashes can be used to continue lines:

FOO = \
     bar \
     baz

A variable substitution looks like this:

  $(FOO)

A typical use of variables would be something like:

TCL_FILES = main.tcl update.tcl parse.tcl
tclIndex: $(TCL_FILES)
        auto_mkindex [pwd] $^

When tclmake processes a rule or a command, it substitutes variable definitions wherever possible. In this example, the effect is exactly the same as for the rule in the Introduction. The variable $^ stands for all the dependencies of the rule -- see Commands.

Variables are defined recursively, as in make. For example, in the following,

FOO = $(BAR) foo!
BAR = oh

the value of FOO will be "oh foo!".

Environment variables can be referenced in the same way. A variable defined in a makefile or on the command line will override the value given by the environment. tclmake can also read variable definitions from regular makefiles, with a command such as

use makefile

tclmake defines some variables automatically:

MAKE

The command used to invoke it. This is always set to "tclmake," so that it can be used to run a sub-make.

MAKEDIR

The directoryon which tclmake is running.

MAKEFLAG

The flags passed to tclmake on the command line.

MAKEVARS

The variables passed to tclmake on the command line.

tclmake does not support non-recursively-defined variables, as in the := definitions of GNU make.