Integrating the JHDL Design Environment into Ptolemy II
Michael J. Wirthlin, Brigham Young University
wirthlin@ee.byu.edu
JHDL is structural design approach based on Java for creating high-performance FPGA-based designs. Users design circuits by instantiating circuit "objects" and interconnecting them with corresponding wire objects. While JHDL has been used to create many large circuits, design with JHDL occurs a relatively low-level (i.e. FPGA primitives and optimized design libraries). To facilitate the design of complex signal processing systems, the JHDL simulator has been integrated into the Ptolemy-II modeling environment. Ptolemy is used to provide a rich testbench facility (including signal generators and signal graph package) and a high-level modeling environment using the SDF domain. Using Ptolemy and JHDL together, users may define high-level signal processing systems in SDF and refine them by inserting appropriate JHDL circuit generators.