Precision Timed (PRET) Machines

We argue that at least for embedded software applications, computer architecture, software, and networking have gone too far down the path of emphasizing average case performance over timing predictability. In architecture, techniques such as multi-level caches and deep pipelines with dynamic dispatch and speculative execution make worst-case execution times (WCET) highly dependent on both implementation details of the processor and on the context in which the software is executed. Yet virtually all real-time programming methodologies depend on WCET. When timing properties are important in the software and when concurrent execution is affected by timing, the result is brittle design.

The goal of this project is to reintroduce timing predictability and repeatability by judiciously adopting architectural optimization techniques to deliver performance enhancements without sacrificing timing predictability and repeatability. Our approach includes extending the instruction-set architectures (ISA) with control over execution time. We have demonstrated that timing predictability and repeatability are not at odds with performance.

This project produced three generations of PRET machines, the latest of which is an extension of the open-source RISC V architecture. This implementation, called FlexPRET, offers a configurable architecture that can mix hard real-time functions with repeatable timing and non-real-time performance-sensitive applications. At one extreme of the configuration, the processor is a conventional RISC V with competitive performance, and at the other extreme it is hard real-time processor with precise and repeatable timing. Intermediate configurations support mixed criticality applications.

By providing simulators and softcores realized on FPGAs, we have also shown that PRET architectures executing software components can be seamlessly integrated with what would traditionally have been purely hardware designs, thus greatly improving the expressiveness and usability of FPGA-based design flows.

PRET provides a starting point for a revolution that will make timing predictability and repeatability central features of embedded processors.

Software

• April, 2014 - FlexPRET Verilog softcore and C++ simulator

  A new processor called FlexPRET, especially designed for mixed-criticality systems, has been released and presented at RTAS 2014, April 15-17, in Berlin, Germany. The paper is available here. The processor is written in Chisel, which generates both Verilog code and C++ simulator for various configurations.

• May, 2011 - PTARM C++ Simulator.

  We have released a cycle accurate model of our PTARM softcore for users that wish to quickly prototype the PRET architecture. Serial communication is simulated through the terminal, and main memory interactions go through the predictable DRAM controller. Programs are again written in C and compiled using the gnu-arm cross compiler.

• September, 2010 - PTARM VHDL Softcore.

  We have constructed a FPGA softcore of our architecture using ARM as our instruction set architecture (Precision Timed ARM - PTARM). The core is synthesized on a Xilinx Virtex5 FPGA on a ml505 evaluation board. The core includes a UART controller, which can be used to communicate through the serial port on the board. It also contains a DVI controller to output to a LCD monitor through the DVI port. We also include a predictable memory controller to communicate with a DRAM. Programs can be written in C and compiled using the gnu-arm cross compiler and loaded onto the core.

• February, 2009 - SPARC C++ Simulator

  We have released a cycle-accurate model and simulator of a thread interleaved PRET architecture based on the SPARC ISA. The architecture has multiple software-managed on-chip memories, a memory wheel to arbitrate access to main memory, and extensions to the ISA with timing instructions. Programs are written in C and compiled using GCC’s SPARC compiler. We provide examples, including a video graphic driver example and RSA encryption/decryption algorithms to avoid timing-channel attacks.

People

Publications

1. Edward A. Lee, Jan Reineke, and Michael Zimmer, "Abstract PRET Machines," Invited TCRTS award paper. IEEE Real-Time Systems Symposium (RTSS 17), December 5, 2017. (See also Preprint)
2. Sam Zamani, Investigation of using a PRET processor on a low-cost, low- power FPGA, KTH, School of Information and Communication Technology (ICT), Independent thesis Basic level (professional degree), 2016.
3. Michael Zimmer, "Predictable Processors for Mixed-Criticality Systems and Precision-Timed I/O, PhD Thesis, EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2015-181, August 10, 2015.
4. Hokeun Kim, David Broman, Edward A. Lee, Michael Zimmer, Aviral Shrivastava, and Junkwang Oh, A Predictable and Command-Level Priority-Based DRAM Controller for Mixed-Criticality Systems, in Proceedings of the 21st IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), Seattle, pp 317-326, WA, USA, April 13-16, 2015.
5. Edward A. Lee, "The Past, Present, and Future of Cyber-Physical Systems: A Focus on Models," Sensors, 15(3), p. 4837-4869, doi:10.3390/s150304837, February, 2015 (open access).
6. Michael Zimmer, David Broman, Chris Shaver, and Edward A. Lee. FlexPRET: A Processor Platform for Mixed-Criticality Systems, In Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), Berlin, Germany, April 15-17, 2014.
7. Yooseong Kim, David Broman, Jian Cai, and Aviral Shrivastava. WCET-Aware Dynamic Code Management on Scratchpads for Software-Managed Multicores, In Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), Berlin, Germany, April 15-17, 2014.
8. Eugene Yip, Matthew Kuo, Partha Roop, and David Broman. Relaxing the Synchronous Approach for Mixed-Criticality Systems, In Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), Berlin, Germany, April 15-17, 2014.
9. Jan Reinecke, Johannes Doerfert Architecture-Parametric Timing Analysis, In Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), Richard West (ed.), IEEE 189-200, April, 2014.
10. Insa Fuhrmann, David Broman, Steven Smyth and Reinhard von Hanxleden Towards Interactive Timing Analysis for Designing Reactive Systems, EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2014-26, April 3, 2014.
11. David Broman, Michael Zimmer, Yooseong Kim, Hokeun Kim, Jian Cai, Aviral Shrivastava, Stephen A. Edwards, Edward A. Lee. Precision Timed Infrastructure: Design Challenges. In Proceedings of the Electronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31-June 1, 2013.
12. David Broman. High-Confidence Cyber-Physical Co-Design, Proceedings of the Work-in-Progress (WiP) session of the 33rd IEEE Real-Time Systems Symposium (RTSS 2012), Page 12, San Juan, Puerto Rico, December, 2012.
13. Isaac Liu, Jan Reineke, David Broman, Michael Zimmer, Edward A. Lee. A PRET Microarchitecture Implementation with Repeatable Timing and Competitive Performance, In Proceedings of the 30th IEEE International Conference on Computer Design (ICCD), Pages 87-93, October, 2012.
14. Isaac Liu. Precision Timed Machines, Ph.D. Dissertation, EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2012-113, May 14, 2012.
15. Isaac Liu, Edward A. Lee, Matthew Viele, Guoqiang Gerald Wang, Hugo Andrade. A Heterogeneous Architecture for Evaluating Real-Time One-Dimensional Computational Fluid Dynamics on FPGAs, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Toronto, Canada, April 29-May 1, 2012.
16. Jan Reineke, Isaac Liu, Hiren D. Patel, Sungjun Kim, Edward A. Lee, PRET DRAM Controller: Bank Privatization for Predictability and Temporal Isolation, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October, 2011.
17. Dai Nguyen Bui, Edward A. Lee, Isaac Liu, Hiren D. Patel, Jan Reineke. Temporal Isolation on Multiprocessing Architectures, Design Automation Conference (DAC), June, 2011.
18. Isaac Liu, Jan Reineke, and Edward A. Lee. A PRET Architecture Supporting Concurrent Programs with Composable Timing Properties, 44th Asilomar Conference on Signals, Systems, and Computers, November 2010.
19. Dai Bui, Hiren D. Patel, and Edward A. Lee, Deploying Hard Real-time Control Software on CMPs, Proceedings of International Conference on Embedded and Real-time Computing Systems and Applications (RTCSA), 2010.
20. Martin Schoeberl, Hiren D. Patel, Edward A. Lee. Fun with a Deadline Instruction, EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2009-149, October 30, 2009.
21. Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Isaac Liu, Hiren D. Patel, Martin Schoeberl. A Disruptive Computer Design Idea: Architectures with Repeatable Timing, Proceedings of International Conference on Computer Design (ICCD), IEEE, Lake Tahoe, CA, 4-7 October, 2009.
22. Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Hiren D. Patel, Martin Schoeberl. Reconciling Repeatable Timing with Pipelining and Memory Hierarchy, Workshop on Reconciling Performance and Predictability, Grenoble, France, October 15, 2009.
23. Shanna-Shaye Forbes, Ben Lickly, Man-Kit Leung C Code Generation from the Giotto Model of Computation to the PRET Architecture, Technical Report No. UCB/EECS-2009-86, May, 2009
24. Devesh Dedhia, Example application under PRET environment -- Programming a MultiMediaCard, Computer Science Technical Report CUCS-005-09, Columbia University.
25. Isaac Liu and David McGrogan. Elimination of Side Channel Attacks on a Precision Timed Architecture, Technical Report No. UCB/EECS-2009-15, January 26, 2009
26. Nishant R. Shah, Memory issues in PRET machines, Computer Science Technical Report CUCS-059-08, Columbia University, December, 2008.
27. Hiren D. Patel, Ben Lickly, Bas Burgers and Edward A. Lee, A Timing Requirements-Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture, Technical Report No. UCB/EECS-2008-115, September, 2008
28. Shanna-Shaye Forbes, Hugo A. Andrade, Hiren D. Patel and Edward A. Lee. An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture, In proceedings of the 12-th IEEE International Symposium on Distributed Simulation and Real Time Applications (DSRT), October, 2008.
29. Ben Lickly, Isaac Liu, Sungjun Kim, Hiren D. Patel, Stephen A. Edwards and Edward A. Lee, Predictable Programming on a Precision Timed Architecture, in proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), October, 2008.
30. Ben Lickly, Isaac Liu, Sungjun Kim, Hiren D. Patel, Stephen A. Edwards and Edward A. Lee, Predictable Programming on a Precision Timed Architecture, Technical Report No. UCB/EECS-2008-40, April, 2008.
31. Stephen A. Edwards and Edward A. Lee, The case for Precision Timed (PRET) Machines, in proceedings of the 44th annual conference on Design Automation Conference, San Diego, California.
32. Stephen A. Edwards and Edward A. Lee. The Case for the Precision Timed (PRET) Machine, Technical report, University of California, Berkeley, UCB/EECS-2006-149, November, 2006.
33. Edward A. Lee, The Case for Precision Timed (PRET) Machines, National Workshop on High-Confidence Software Platforms for Cyber-Physical Systems (HCSP-CPS) Arlington, VA, November 30, 2006

Presentations

1. David Broman, Stephen A. Edwards, and Edward A. Lee, Precision Timed Infrastructure: Promoting Time to a First-Class Citizen in System Design, National Workshop on the New Clockwork for Time-Critical Systems, Baltimore, October 26, 2012.
2. David Broman, Precision Timed Infrastructure - Making Time an Engineering Abstraction, 52nd IFIP WG 2.4 Meeting, Vadstena, Sweden, May 22, 2012.
3. Jan Reineke, Timing Analysis of Embedded Software for Families of Microarchitectures, MuSyC Review Meeting, Berkeley, CA, November 2011.
4. Jan Reineke, PRET DRAM Controller: Bank Privatization for Predictability and Temporal Isolation, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Taipei, Taiwan, October 2011.
5. Jan Reineke. To Meet or Not to Meet the Deadline, Ninth Biennial Ptolemy Miniconference, Berkeley, CA, February 16, 2011.
6. Edward A. Lee, A Disruptive Computer Design Idea: Architectures with Repeatable Timing, IEEE International Conference on Computer Design(ICCD), Squaw Valley, CA, October 6, 2009.
7. Edward A. Lee, Architectures with repeatable timing for Cyber-Physical Systems, Workshop on Cyber Physical Systems, Grenoble, France, October 16, 2009
8. Stephen A. Edwards, Reconciling Repeatable Timing with Pipelining and Memory Hierarchy, Workshop on Reconciling Performance with Predictability (RePP), Grenoble, France, October 15, 2009
9. Hiren D. Patel, Predictable Programming on a Precision Timed Architecture, International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), Atlanta, Georgia, October 21, 2008.
10. Hiren D. Patel, Predictable Programming on a Precision Timed Architecture, Virginia Tech., Blacksburg, Virginia, October 17, 2008.
11. Stephen Edwards, What We Do With 10^12 Transistors?, Google, Mountain View, California, February 20, 2008. [video]
12. Stephen Edwards, Precision Timed (PRET) Machines, Altera, San Jose, California, January 9, 2008.
13. Stephen Edwards, Precision Timed (PRET) Machines, National Taiwan University, Taipei, Taiwan, July 6, 2007.
14. Stephen Edwards, Precision-Timed (PRET) Machines at DAC is mentioned in the EETimes article, "Designers pitch 'wild and crazy' ideas at DAC.", June 6, 2007.
15. Stephen A. Edwards and Edward A. Lee. Precision-Timed (PRET) Machines, June, 2007; Presented at the 44th Design Automation Conference, San Diego, California.

Posters

1. Isaac Liu, Ben Lickly, Hiren D. Patel, Edward A. Lee, Poster Abstract: Timing Instructions - ISA Extensions for Timing Guarantees, a poster at Real-Time and Embedded Technology and Applications Symposium, San Francisco, California, 2009.
2. Ben Lickly and Hiren D. Patel, Timing-aware Exceptions for a Precision Timed (PRET) Target, Berkeley EECS Annual Research Symposium, February 12, 2009.
3. Hiren D. Patel, Isaac Liu, Ben Lickly, and Edward A. Lee, A Precision Timed Architecture for Predictable and Repeatable Timing, Berkeley EECS Annual Research Symposium, February 12, 2009.
4. Shanna-Shaye Forbes, Hiren D. Patel, Hugo A. Andrade, Ben Lickly, Isaac Liu. Mapping a Timed Functional Specification to a Precision Timed (PRET) Machine, Talk or presentation, 21, 2008.

Class Projects

1. Shanna-Shaye Forbes, Toward an Automated Mapping from A Timed Functional Specification to A Timed Architecture, EE 249: Design of Embedded Systems: Models, Validation and Synthesis, Fall 2007.
2. Isaac Liu and Joern Rheder, A Multithreaded Peripheral Processor for Real-Time Embedded Systems, EE 252: Graduate Computer Architecture, Fall 2007.
3. Isaac Liu and Ben Lickly, Micro-Architectural modeling of a SPARC Processor, EE 249: Design of Embedded Systems: Models, Validation and Synthesis, Fall 2007.

Miscellaneous

• C++ Coding guidelines
• Assigned Readings and Reviews

Wiki

• Internal Wiki accessible only by Chess participants and PRET members.

Resources

• Membership in pret is open to Chess participants (see Who can get an account?).
  Request an account in the pret workgroup
• pret private forum (Open only to pret workgroup members)

Mailing lists and discussion forums may be found under the pret link above.

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Acknowledgments

This work was supported in part by the Center for Hybrid and Embedded Software Systems (CHESS) at UC Berkeley, which receives support from the National Science Foundation (NSF awards \#1446619 (Mathematical Theory of CPS), \#1329759 (COSMOI), and \#0931843 (ActionWebs), the Naval Research Laboratory (NRL \#N0013-12-1-G015), and the following companies: Denso, National Instruments, and Toyota.

Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of any of the sponsors.