Citation
Trevor Meyerowitz, Dominik Langen, Mirko Sauermann, Alberto Sangiovanni-Vincentelli. "Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor". Design Automation Test Europe, IEEE, March, 2008.

Abstract
A generic and retargetable tool flow is presented that enables the export of timing data from software running on a cycle-accurate Virtual Prototype (VP) to a concurrent functional simulator. First, an annotation framework takes information gathered from running an application on the VP and automatically annotates the line-level delays back to the original source code. Then, a SystemC-based timed functional simulator runs the annotated source code much faster than the VP while preserving timing accuracy. This simulator is API-compatible with the multiprocessor's operating system. Therefore, it can compile and run unmodified applications on the host PC. This flow has been implemented for MuSIC(Multiple SIMD Cores), a heterogeneous multiprocessor developed at Infineon to support Software Defined Radio (SDR). When compared with an optimized cycle-accurate VP of MuSIC on a variety of tests, including a multiprocessor JPEG encoder, the accuracy is within 20%, with speedups from 10x to 1000x.

Electronic downloads

• annotation_paper_final.pdf · application/pdf · 278 kbytes

• HTML

  Trevor Meyerowitz, Dominik Langen, Mirko Sauermann, Alberto
  Sangiovanni-Vincentelli. <a
  href="http://chess.eecs.berkeley.edu/pubs/459.html"
  >Source-Level Timing Annotation and Simulation for a
  Heterogeneous Multiprocessor</a>, Design Automation
  Test Europe, IEEE, March, 2008.

• Plain text

  Trevor Meyerowitz, Dominik Langen, Mirko Sauermann, Alberto
  Sangiovanni-Vincentelli. "Source-Level Timing
  Annotation and Simulation for a Heterogeneous
  Multiprocessor". Design Automation Test Europe, IEEE,
  March, 2008.

• BibTeX

  @inproceedings{MeyerowitzLangenSauermannSangiovanniVincentelli08_SourceLevelTimingAnnotationSimulationForHeterogeneous,
      author = {Trevor Meyerowitz and Dominik Langen and Mirko
                Sauermann and Alberto Sangiovanni-Vincentelli},
      title = {Source-Level Timing Annotation and Simulation for
                a Heterogeneous Multiprocessor},
      booktitle = {Design Automation Test Europe},
      organization = {IEEE},
      month = {March},
      year = {2008},
      abstract = {A generic and retargetable tool flow is presented
                that enables the export of timing data from
                software running on a cycle-accurate Virtual
                Prototype (VP) to a concurrent functional
                simulator. First, an annotation framework takes
                information gathered from running an application
                on the VP and automatically annotates the
                line-level delays back to the original source
                code. Then, a SystemC-based timed functional
                simulator runs the annotated source code much
                faster than the VP while preserving timing
                accuracy. This simulator is API-compatible with
                the multiprocessor's operating system. Therefore,
                it can compile and run unmodified applications on
                the host PC. This flow has been implemented for
                MuSIC(Multiple SIMD Cores), a heterogeneous
                multiprocessor developed at Infineon to support
                Software Defined Radio (SDR). When compared with
                an optimized cycle-accurate VP of MuSIC on a
                variety of tests, including a multiprocessor JPEG
                encoder, the accuracy is within 20%, with speedups
                from 10x to 1000x.},
      URL = {http://chess.eecs.berkeley.edu/pubs/459.html}
  }
  

Posted by Trevor Meyerowitz on 23 Jun 2008.
Groups: chess
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