Citation
Edward A. Lee, Stephen A. Edwards, Isaac Liu, Sungjun Kim, Hiren Patel, Martin Schoeberl. "Architectures with repeatable timing for Cyber-Physical Systems". Talk or presentation, 16, October, 2009; Invited Keynote talk, Workshop on Cyber Physical Systems (part of ES week) Grenoble, France.

Abstract
This presentation argues that repeatable timing is more important and more achievable than predictable timing. It describes microarchitecture approaches to pipelining and memory hierarchy that deliver repeatable timing and promise comparable or better performance compared to established techniques. Specifically, threads are interleaved in a pipeline to eliminate pipeline hazards, and a hierarchical memory architecture is outlined that hides memory latencies.

Electronic downloads

• PRET_WCPS.pdf · application/pdf · 2541 kbytes

• HTML

  Edward A. Lee, Stephen A. Edwards, Isaac Liu, Sungjun Kim,
  Hiren Patel, Martin Schoeberl. <a
  href="http://chess.eecs.berkeley.edu/pubs/648.html"
  ><i>Architectures with repeatable timing for
  Cyber-Physical Systems</i></a>, Talk or
  presentation,  16, October, 2009; Invited Keynote talk,
  Workshop on Cyber Physical Systems (part of ES week)
  Grenoble, France.

• Plain text

  Edward A. Lee, Stephen A. Edwards, Isaac Liu, Sungjun Kim,
  Hiren Patel, Martin Schoeberl. "Architectures with
  repeatable timing for Cyber-Physical Systems". Talk or
  presentation,  16, October, 2009; Invited Keynote talk,
  Workshop on Cyber Physical Systems (part of ES week)
  Grenoble, France.

• BibTeX

  @presentation{LeeEdwardsLiuKimPatelSchoeberl09_ArchitecturesWithRepeatableTimingForCyberPhysicalSystems,
      author = {Edward A. Lee and Stephen A. Edwards and Isaac Liu
                and Sungjun Kim and Hiren Patel and Martin
                Schoeberl},
      title = {Architectures with repeatable timing for
                Cyber-Physical Systems},
      day = {16},
      month = {October},
      year = {2009},
      note = {Invited Keynote talk, Workshop on Cyber Physical
                Systems (part of ES week)
  Grenoble, France},
      abstract = {This presentation argues that repeatable timing is
                more important and more achievable than
                predictable timing. It describes microarchitecture
                approaches to pipelining and memory hierarchy that
                deliver repeatable timing and promise comparable
                or better performance compared to established
                techniques. Specifically, threads are interleaved
                in a pipeline to eliminate pipeline hazards, and a
                hierarchical memory architecture is outlined that
                hides memory latencies.},
      URL = {http://chess.eecs.berkeley.edu/pubs/648.html}
  }
  

Posted by Isaac Liu on 11 Jan 2010.
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