Citation
Isaac Liu, Jan Reineke. "A PRET Architecture Supporting Concurrent Programs with Composable Timing Properties". Talk or presentation, 16, February, 2011; Poster presented at the Ninth Biennial Ptolemy Miniconference, Berkeley, CA.

Abstract
In order to improve design time and efficiency of systems, large scale system design is often split into the design of separate functions, which are later integrated together. For real time safety critical applications, the ability to separately verify timing properties of functions is important. If the integration of functions on a particular platform destroys the timing properties of individual functions, then it is not possible to verify timing properties separately. Modern computer architectures introduce timing interference between functions due to unrestricted access of shared hardware resources, such as pipelines and caches. Thus, it is difficult, if not impossible, to integrate two functions on a modern computer architecture while preserving their separate timing properties. This paper describes a realization of PRET, a class of computer architectures designed for timing predictability. Our realization employs a thread-interleaved pipeline with scratchpad memories, and has a predictable DRAM controller. It decouples execution of multiple hardware contexts on a shared hardware platform, which allows for a straight forward integration of different functions onto a shared platform.

Electronic downloads

• p06liu_BEARS2011_PtolemyMiniConf_PRET.ppt.pdf · application/pdf · 449 kbytes

• HTML

  Isaac Liu, Jan Reineke. <a
  href="http://chess.eecs.berkeley.edu/pubs/821.html"><i>A
  PRET Architecture Supporting Concurrent Programs with
  Composable Timing Properties</i></a>, Talk or
  presentation,  16, February, 2011; Poster presented at the
  <a
  href="http://ptolemy.eecs.berkeley.edu/conferences/11"
  >Ninth Biennial Ptolemy Miniconference</a>,
  Berkeley, CA.

• Plain text

  Isaac Liu, Jan Reineke. "A PRET Architecture Supporting
  Concurrent Programs with Composable Timing Properties".
  Talk or presentation,  16, February, 2011; Poster presented
  at the <a
  href="http://ptolemy.eecs.berkeley.edu/conferences/11"
  >Ninth Biennial Ptolemy Miniconference</a>,
  Berkeley, CA.

• BibTeX

  @presentation{LiuReineke11_PRETArchitectureSupportingConcurrentProgramsWithComposable,
      author = {Isaac Liu and Jan Reineke},
      title = {A PRET Architecture Supporting Concurrent Programs
                with Composable Timing Properties},
      day = {16},
      month = {February},
      year = {2011},
      note = {Poster presented at the <a
                href="http://ptolemy.eecs.berkeley.edu/conferences/11"
                >Ninth Biennial Ptolemy Miniconference</a>,
                Berkeley, CA.},
      abstract = {In order to improve design time and efficiency of
                systems, large scale system design is often split
                into the design of separate functions, which are
                later integrated together. For real time safety
                critical applications, the ability to separately
                verify timing properties of functions is
                important. If the integration of functions on a
                particular platform destroys the timing properties
                of individual functions, then it is not possible
                to verify timing properties separately. Modern
                computer architectures introduce timing
                interference between functions due to unrestricted
                access of shared hardware resources, such as
                pipelines and caches. Thus, it is difficult, if
                not impossible, to integrate two functions on a
                modern computer architecture while preserving
                their separate timing properties. This paper
                describes a realization of PRET, a class of
                computer architectures designed for timing
                predictability. Our realization employs a
                thread-interleaved pipeline with scratchpad
                memories, and has a predictable DRAM controller.
                It decouples execution of multiple hardware
                contexts on a shared hardware platform, which
                allows for a straight forward integration of
                different functions onto a shared platform.},
      URL = {http://chess.eecs.berkeley.edu/pubs/821.html}
  }
  

Posted by Christopher Brooks on 18 Feb 2011.
Groups: ptolemy
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