Citation
Vigyan Singhal. "Deploying Formal in a Simulation World". Talk or presentation, 17, October, 2011.

Abstract
Missing bugs in hardware designs is expensive enough that the semiconductor industry routinely spends 2/3 of the design cycle in verifying the designs before tapeout. Formal verification technology has today advanced to the stage that it can complement or replace simulation effort for selected hardware designs. However, the adoption of formal in a chip design schedule requires (a) Planning, and deciding where to apply formal; (b) Verifying efficiently, often through the use of manually crafted abstractions; and (c) Measuring coverage at the end of the verification process, to determine how much was formally verified so fit the formal effort in the context of the popular simulation-based coverage metrics.

Electronic downloads

• singhal-formal-cal-101711.pdf · application/pdf · 870 kbytes

• HTML

  Vigyan Singhal. <a
  href="http://chess.eecs.berkeley.edu/pubs/889.html"
  ><i>Deploying Formal in a Simulation
  World</i></a>, Talk or presentation,  17,
  October, 2011.

• Plain text

  Vigyan Singhal. "Deploying Formal in a Simulation
  World". Talk or presentation,  17, October, 2011.

• BibTeX

  @presentation{Singhal11_DeployingFormalInSimulationWorld,
      author = {Vigyan Singhal},
      title = {Deploying Formal in a Simulation World},
      day = {17},
      month = {October},
      year = {2011},
      abstract = {Missing bugs in hardware designs is expensive
                enough that the semiconductor industry routinely
                spends 2/3 of the design cycle in verifying the
                designs before tapeout. Formal verification
                technology has today advanced to the stage that it
                can complement or replace simulation effort for
                selected hardware designs. However, the adoption
                of formal in a chip design schedule requires (a)
                Planning, and deciding where to apply formal; (b)
                Verifying efficiently, often through the use of
                manually crafted abstractions; and (c) Measuring
                coverage at the end of the verification process,
                to determine how much was formally verified so fit
                the formal effort in the context of the popular
                simulation-based coverage metrics.},
      URL = {http://chess.eecs.berkeley.edu/pubs/889.html}
  }
  

Posted by Patricia Derler on 2 Feb 2012.
Groups: chessworkshop
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