IRSIM

  Figure 2 shows the relative performance of various machines for this application. We observe that increasing the circuit size does not have too much effect on the performance ratio. This is because the circuit is dynamically partitioned into stages and computation is performed on each stage separately. These stages are typically small and fit the first level cache of the machines. The instructions performed are mostly floating point. Hence, L-1 cache size and access time and the floating point unit are the major factors in determining the performance. 21064_182, which has the smallest L-1 cache access time, was found to be consistently the fastest machine. The i586_120 and the Sparc20_100 were found to have comparable performance due to their similar L-1 access time. R4400_60 and Sparc10_50 were found to be the slowest.