This application is highly memory intensive. As mentioned earlier, the underlying data structure (BDDs) can be manipulated with either random or local memory access behavior. We make use of two BDD packages - CMU [9] and CAL [10] which have random and local memory access patterns respectively, to get two sets of results. The inputs were taken from MCNC and ISCAS benchmark sets. The performance ratios are shown in Figure 2. In the case of random memory access behavior, we would expect that the memory organization of an architecture would have a bigger role than the clock rate in determining the performance. From the graph we observe that Sparc20_100 and i586_120 both outperform 21064_182 for larger inputs. The reason for this behavior is the lower second level access time for Sparc20_100. As expected, localized memory access makes CPU speed a dominating factor in the performance. As seen in Figure 2, 21064_182 far outperforms all other architectures. R4400_60 with minimum clock rate performs the worst on almost all the examples.