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00008 #ifndef DESTIP_H_
00009 #define DESTIP_H_
00010
00011 #include "systemc.h"
00012 #include <map>
00013 #include <sstream>
00014
00015 template< int FlitWidth >
00016 class DestIp : public sc_module
00017 {
00018 public:
00019
00020 sc_in< sc_bv< FlitWidth > > DataIn ;
00021 sc_in< bool > ValidIn ;
00022 sc_out< bool > AckOut ;
00023 sc_out< bool > FullOut ;
00024 sc_in< bool > Clock ;
00025
00026 SC_HAS_PROCESS( DestIp ) ;
00027
00028 DestIp( sc_module_name n , int pId ) : sc_module( n ) {
00029
00030 mState = IDLE ;
00031 mRstate = VALID ;
00032 mId = pId ;
00033
00034 SC_THREAD( Fsm ) ;
00035 sensitive_pos << Clock ;
00036
00037 cout << "Destination " << name() << " initialized" << endl ;
00038
00039 }
00040
00041 void Fsm( ) ;
00042
00043 void Report( ) ;
00044
00045 string GetLatencies( ) ;
00046 string GetBandwidths( ) ;
00047
00048 map< int , int > GetReceivedBits( ) ;
00049
00050 enum{ IDLE , FLIT } mState ;
00051 enum{ VALID , RX } mRstate ;
00052
00053 int mId ;
00054
00055 map< int , int > mReceivedBits ;
00056
00057 map< int , double > mLatencies ;
00058
00059 double GetAverageLatency( ) ;
00060 double GetMinLatency( ) ;
00061 double GetMaxLatency( ) ;
00062 int mPacketSize ;
00063 int mFlitCount ;
00064 int mCurrentSource ;
00065 int mCurrentDest ;
00066
00067 sc_bv< FlitWidth > mCurrentIn ;
00068
00069 } ;
00070
00071 template< int FlitWidth >
00072 void DestIp< FlitWidth >::Fsm( )
00073 {
00074
00075 cout << "Destination " << name( ) << " running " << endl ;
00076
00077 FullOut = false ;
00078
00079 AckOut = false ;
00080
00081 while( true ) {
00082 wait( ) ;
00083
00084 switch( mState ) {
00085 case IDLE :
00086
00087 switch( mRstate ) {
00088 case VALID :
00089 if ( ValidIn ) {
00090 mCurrentIn = DataIn ;
00091 mCurrentSource = ( mCurrentIn.range( 7 , 0 ) ).to_int( ) ;
00092 mCurrentDest = ( mCurrentIn.range( 15 , 8 ) ).to_int( ) ;
00093 mPacketSize = ( mCurrentIn.range( 23 , 16 ) ).to_int( ) ;
00094 mFlitCount = mPacketSize - 1 ;
00095
00096 if ( mReceivedBits.find( mCurrentSource ) == mReceivedBits.end( ) ) {
00097 mReceivedBits[ mCurrentSource ] = FlitWidth ;
00098 } else {
00099 mReceivedBits[ mCurrentSource ] = mReceivedBits[ mCurrentSource ] + FlitWidth ;
00100 }
00101 mRstate = RX ;
00102 AckOut = true ;
00103 }
00104 break ;
00105 case RX :
00106 AckOut = false ;
00107 mRstate = VALID ;
00108 mState = FLIT ;
00109 break ;
00110 }
00111 break;
00112 case FLIT :
00113 switch( mRstate ) {
00114 case VALID :
00115 if ( ValidIn ) {
00116 mFlitCount -- ;
00117
00118 mReceivedBits[ mCurrentSource ] = mReceivedBits[ mCurrentSource ] + FlitWidth ;
00119
00120 if( mFlitCount == 0 ) {
00121 if ( mLatencies.find( mCurrentSource ) == mLatencies.end( ) ){
00122 mCurrentIn = DataIn ;
00123 mLatencies[mCurrentSource] = sc_simulation_time( ) - mCurrentIn.to_int( ) ;
00124 } else {
00125 mCurrentIn = DataIn ;
00126 mLatencies[mCurrentSource] += sc_simulation_time( ) - mCurrentIn.to_int( ) ;
00127 }
00128 }
00129 mRstate = RX ;
00130 AckOut = true ;
00131 }
00132 break ;
00133 case RX :
00134 AckOut = false ;
00135 mRstate = VALID ;
00136 if( mFlitCount == 0 ) {
00137 mState = IDLE ;
00138 }else{
00139 mState = FLIT ;
00140 }
00141 break ;
00142 }
00143 break;
00144 }
00145 }
00146 }
00147
00148
00149 template< int FlitWidth >
00150 map< int , int > DestIp< FlitWidth >::GetReceivedBits( ) {
00151 return mReceivedBits;
00152 }
00153
00154
00155 template< int FlitWidth >
00156 void DestIp< FlitWidth >::Report( ) {
00157
00158
00159 cout << "Bandwidth report for " << name( ) << endl ;
00160 map<int,int>::iterator It ;
00161 for( It = mReceivedBits.begin( ) ; It != mReceivedBits.end( ) ; It++ ) {
00162 cout << "\t Average bandwidth from source " << It->first << " = " << It->second /( sc_simulation_time( ) *1e-9 ) << endl ;
00163 }
00164
00165 cout << "Delay report for " << name( ) << endl ;
00166 map<int,double>::iterator Lit ;
00167 for( Lit = mLatencies.begin( ) ; Lit != mLatencies.end( ) ; Lit++ ) {
00168 cout << "\t Average latency from source " << Lit->first << " = " << FlitWidth * Lit->second / ( double )mReceivedBits[Lit->first] << endl ;
00169 }
00170
00171 }
00172
00173 template< int FlitWidth >
00174 string DestIp< FlitWidth >::GetLatencies( ) {
00175 stringstream s ;
00176 map<int,double>::iterator Lit ;
00177 for( Lit = mLatencies.begin( ) ; Lit != mLatencies.end( ) ; Lit++ ) {
00178 s << FlitWidth * Lit->second / ( double )mReceivedBits[Lit->first] << endl ;
00179 }
00180 return s.str() ;
00181
00182 }
00183
00184 template< int FlitWidth >
00185 string DestIp< FlitWidth >::GetBandwidths( ) {
00186 stringstream s ;
00187
00188 map<int,int>::iterator It ;
00189 for( It = mReceivedBits.begin( ) ; It != mReceivedBits.end( ) ; It++ ) {
00190 s << It->second /( sc_simulation_time( ) *1e-9 ) << endl ;
00191 }
00192
00193 return s ;
00194 }
00195
00196 template< int FlitWidth >
00197 double DestIp< FlitWidth >::GetAverageLatency( ) {
00198
00199 map<int,double>::iterator Lit ;
00200 double Average = 0 ;
00201 for( Lit = mLatencies.begin( ) ; Lit != mLatencies.end( ) ; Lit++ ) {
00202 Average+= FlitWidth * Lit->second / ( double ) mReceivedBits[Lit->first] ;
00203 }
00204 return Average/(double)( mLatencies.size( ) ) ;
00205
00206 }
00207
00208 template< int FlitWidth >
00209 double DestIp< FlitWidth >::GetMinLatency( ) {
00210
00211 map<int,double>::iterator Lit ;
00212 double Min = DBL_MAX ;
00213 for( Lit = mLatencies.begin( ) ; Lit != mLatencies.end( ) ; Lit++ ) {
00214 if ( FlitWidth * Lit->second / ( double ) mReceivedBits[Lit->first] < Min ) {
00215 Min = FlitWidth * Lit->second / ( double ) mReceivedBits[Lit->first] ;
00216 }
00217 }
00218 return Min ;
00219
00220 }
00221
00222 template< int FlitWidth >
00223 double DestIp< FlitWidth >::GetMaxLatency( ) {
00224
00225 map<int,double>::iterator Lit ;
00226 double Max = 0 ;
00227 for( Lit = mLatencies.begin( ) ; Lit != mLatencies.end( ) ; Lit++ ) {
00228 if ( FlitWidth * Lit->second / ( double ) mReceivedBits[Lit->first] > Max ) {
00229 Max = FlitWidth * Lit->second / ( double ) mReceivedBits[Lit->first] ;
00230 }
00231 }
00232 return Max ;
00233
00234 }
00235
00236
00237
00238 #endif