The older Mescal publications are below available from the Gigascale Systems Research Center (GSRC) to GSRC members. These publications are not publicly available, if you are interested in obtaining a GSRC account and meet the criteria go to the account request page.

Last updated: $Date: 2010-05-18 09:24:12 -0700 (Tue, 18 May 2010) $

• Optimizing the use of GPU Memory in Applications with Large data sets, Nadathur Rajagopalan Satish, Narayanan Sundaram, Kurt Keutzer, International Conference on High Performance Computing (HiPC), 19, December, 2009
• Efficient, High-Quality Image Contour Detection, Bryan Catanzaro, Bor-Yiing Su, Narayanan Sundaram, Yunsup Lee, Mark Murphy, Kurt Keutzer, International Conference on Computer Vision (ICCV), 2, October, 2009
• Scalable HMM based Inference Engine in Large Vocabulary Continuous Speech Recognition, Jike Chong, Youngmin Yi, Ekaterina Gonina, Kurt Keutzer, GSRC Annual Symposium 2009, 3, September, 2009, 1.1.1.15
• Damascene: Highly Parallel Image Contour Detection, Bryan Catanzaro, Narayanan Sundaram, Bor-Yiing Su, Yunsup Lee, Mark Murphy, Kurt Keutzer, GSRC Annual Symposium 2009, 3, September, 2009, 1.1.1.12
• Parallelizing CAD: A Timely Research Agenda for EDA, Bryan Catanzaro, Kurt Keutzer, Bor-Yiing Su, DAC 2008, ACM/IEEE, 12-17, June, 2009
• Damascene: Highly Parallel Image Contour Detection, Bryan Catanzaro, Narayanan Sundaram, Bor-Yiing Su, Yunsup Lee, Mark Murphy, Kurt Keutzer, GSRC Workshop, Dallas TX, 9, March, 2009, 1.1.1.12
• Parallel Scalability> in Speech Recognition: Inference engine in large vocabulary continuous speech recognition, Kisun You, Jike Chong, Youngmin Yi, Ekaterina Gonina, Christopher Hughes, Chen Yen-Kuang, Wonyong Sung, Kurt Keutzer, Signal Processing Magazine Special Issue, 2009
• Compile Time Task and Resource Allocation of Concurrent Applications to Multiprocessor Systems, Nadathur Rajagopalan Satish, University of California, Berkeley, 2009
• Data Parallel Large Vocabulary Continuous Speech Recognition on Graphics Processing Unit, Jike Chong, Youngmin Yi, Nadathur Rajagopalan Satish, Kurt Keutzer, GSRC Annual Symposium 2008, 29, September, 2008, 1.1.1.15
• Fast SVM Training and Classification on a GPU, Bryan Catanzaro, Narayanan Sundaram, Kurt Keutzer, GSRC Annual Symposium 2008, 29, September, 2008, 1.1.1.10.
• Data-Parallel Large Vocabulary Continuous Speech Recognition on Graphics Processors, Jike Chong, Youngmin Yi, Arlo Faria, Nadathur Satish, Kurt Keutzer, Proceedings of the 1st Annual Workshop on Emerging Applications and Many Core Architecture (EAMA), 23-35, June, 2008
• Scheduling Task Dependence Graphs with Variable Task Execution Times onto Heterogeneous Multiprocessors, Nadathur Rajagopalan Satish, Kaushik Ravindran, Kurt Keutzer, University of California, Berkeley, UCB/EECS-2008-42, April, 2008
• Fast Support Vector Machine Training and Classification on Graphics Processors, Bryan Catanzaro, Narayanan Sundaram, Kurt Keutzer, EECS Department, University of California, Berkeley, 11, February, 2008
• Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling, Jike Chong, Nadathur Rajagopalan Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer, Multimedia and Expo, 2007 IEEE International Conference on, 1874-1877, July, 2007
• A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors, Nadathur Rajagopalan Satish, Kaushik Ravindran, Kurt Keutzer, 10th Conference of Design, Automation and Test in Europe (DATE-07), ACM Press, 57-62, April, 2007
• Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design, David Chinnery, Kurt Keutzer, Springer Publishers, 2007, 0387257632
• Deploying Concurrent Applications on Heterogeneous Multiprocessors, Andrew Mihal, University of California, Berkeley, January, 2006
• Automated Mapping of Domain Specific Languages to Application Specific Multiprocessors, William Plishker, University of California, Berkeley, January, 2006
• Sub-RISC Processors, Andrew Mihal, Scott Weber, Kurt Keutzer, Paolo Ienne and Rainer Leupers, 13, 303-338, Elsevier (Book title: Customizable Embedded Processors: Design Technologies and Applications), 2006
• An Automated Exploration Framework for FPGA-Based Soft Multiprocessor Systems, Yujia Jin, Nadathur Rajagopalan Satish, Kaushik Ravindran, Kurt Keutzer, Proceedings of the 2005 International Conference on Hardware/Software Codesign and System Synthesis (CODES-05), pp 273-278, September, 2005
• Using Minimal Minterms to Represent Programmability, Scott Weber, Kurt Keutzer, CODES+ISSS 2005, 63-68, September, 2005
• A Processing Element and Programming Methodology for Click Elements, Andrew Mihal, Kurt Keutzer, Workshop on Application Specific Processors (WASP 2005), 10-17, September, 2005
• Evaluating the Effectiveness of Statistical Gate Sizing for Power Optimization, Nadathur Rajagopalan Satish, Kaushik Ravindran, Matthew W. Moskewicz, David Chinnery, Kurt Keutzer, University of California at Berkeley, ERL Memorandum M05/28, August, 2005
• An FPGA-Based Soft Multiprocessor System for IPv4 Packet Forwarding, Kaushik Ravindran, Nadathur Rajagopalan Satish, Yujia Jin, Kurt Keutzer, 15th International Conference on Field Programmable Logic and Applications (FPL-05), pp 487-492, August, 2005
• Linear Programming for Sizing, Vth and Vdd Assignment, David Chinnery, Kurt Keutzer, International Symposium on Low Power Electronics and Design, 149-154, August, 2005
• Linear Programming for Sizing, Vth and Vdd Assignment, David Chinnery, Kurt Keutzer, August, 2005
• Closing the Power Gap between ASIC and Custom: An ASIC Perspective, David Chinnery, Kurt Keutzer, Design Automation Conference, 275-280, June, 2005
• Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express, Christian Sauer, Matthias Gries, Jennifer Gomez, Kurt Keutzer, M. Franklin, P. Crowley, H. Hadimioglu, P. Onufryk, 4, 55-80, 3, Morgan Kaufmann Publishers, 2005
• Soft Multiprocessor Systems for Network Applications, Yujia Jin, William Plishker, Kaushik Ravindran, Nadathur Rajagopalan Satish, Kurt Keutzer, 21, February, 2005
• Tiny Instruction Processors and Interconnect, Scott Weber, University of California, Berkeley, January, 2005
• Building ASIPs: The Mescal Methodology, Matthias Gries, Kurt Keutzer, Springer, 2005, 0-387-26057-9
• Building ASIPs: The Mescal Methodology, Matthias Gries, Kurt Keutzer, Springer Publishers, 2005, 0387260579
• Methods for Evaluating and Covering the Design Space during Early Design Development, Matthias Gries, Integration, the VLSI Journal, Elsevier, 38, 2, 131-183, December, 2004
• Microarchitecture Modeling for Design-space Exploration, Manish Vachharajani, Princeton University, November, 2004
• APPLICATION-SPECIFIC PROCESSING USING DYNAMICALLY RECONFIGURABLE DATAPATHS, Zhining Huang, Princeton University, November, 2004
• Automated Task Allocation for Network Processors, William Plishker, Kaushik Ravindran, Niraj Shah, Kurt Keutzer, Network System Design Conference Proceedings, 235-245, October, 2004
• Automated Task Allocation for Network Processors, William Plishker, 20, October, 2004
• Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express, Christian Sauer, Matthias Gries, Jennifer Gomez, Scott Weber, Kurt Keutzer, IEEE Int. Conf. on Parallel Computing in Electrical Engineering (PARELEC), 129-134, September, 2004
• NP-Click: A Productive Software Development Approach for Network Processors, Niraj Shah, William Plishker, Kaushik Ravindran, Kurt Keutzer, IEEE Micro, 24, 5, 45-54, September, 2004
• Facilitating Reuse in Hardware Models with Enhanced Type Inference, Manish Vachharajani, Neil Vachharajani, Sharad Malik, David August, Proceedings of The IEEE/ACM/IFIP Second International Conference on Hardware/Software Codesign and System Synthesis, 86-91, September, 2004
• The Liberty Simulation Environment 1.0, Manish Vachharajani, Software, 17, September, 2004
• Fast Cycle-Accurate Simulation and Instruction Set Generation for Constraint-Based Descriptions of Programmable Architectures, Scott Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer, Kurt Keutzer, International Conference on Hardware/Software Codesign (CODES), 18-23, September, 2004
• A Formal Concurrency Model Based Architecture Description Language for Synthesis of Software Development Tools, Wei Qin, S. Rajagopalan, Sharad Malik, ACM 2004 Conference on Languages, Compilers, and Tools for Embedded Systems, 47-56, June, 2004
• The Liberty Structural Specification Language: A High-Level Modeling Language for Component Reuse, Manish Vachharajani, Neil Vachharajani, David August, Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 195-206, June, 2004
• The Design of Dynamically Reconfigurable Datapath Coprocessors, Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo, ACM Transaction in Embedded Computing Systems, 3, 2, May, 2004
• The Liberty Simulation Environment, Version 1.0, Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason Blome, David August, Performance Evaluation Review: Special Issue on Tools for Architecture Research, 31, 4, March, 2004
• Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express, Christian Sauer, Matthias Gries, Jennifer Gomez, Kurt Keutzer, 3rd Workshop on Network Processors (NP3) at the 10th International Symposium on High Performance Computer Architecture (HPCA10), 26-39, February, 2004
• Comparing Network Processor Programming Environments: A Case Study, Niraj Shah, William Plishker, Kurt Keutzer, 2004 Workshop on Productivity and Performance in High-End Computing (P-PHEC), February, 2004
• Automated Task Allocation on Single Chip, Hardware Multithreaded, Multiprocessor Systems, William Plishker, Kaushik Ravindran, Niraj Shah, Kurt Keutzer, Workshop on Embedded Parallel Architectures (WEPA-1), 14-20, February, 2004
• Programming Models for Application-Specific Instruction Processors, Niraj Shah, University of California, Berkeley, January, 2004
• NP-Click: A Programming Model for the Intel IXP1200, Niraj Shah, William Plishker, Kurt Keutzer, P. Crowley, M. Franklin, H. Hadimioglu, P. Onufryk, 9, 181-201, 1, 2, Elsevier, 2004
• The Mescal Architecture Development System (Tipi) Tutorial, Matthias Gries, Scott Weber, Christopher Brooks, Electronics Research Lab, University of California at Berkeley, UCB/ERL M03/40, October, 2003
• Programming Challenges in Network Processor Deployment, Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer, Int. Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 178-187, October, 2003
• Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition, Masayuki Ito, David Chinnery, Kurt Keutzer, 21st International Conference on Computer Design (ICCD'03), October, 2003
• Mescal Languages Reference Manual, Scott Weber, Electronics Research Lab, University of California at Berkeley, UCB/ERL M03/41, October, 2003
• Power Minimization with Multiple Supply Voltages and Multiple Threshold Voltages, D. Chinnery, B. Thompson, M. Orshansky, K. Keutzer, Semiconductor Research Corporation Technical Conference, August, 2003
• Minimization of Dynamic and Static Power Through Joint Assignment of Threshold Voltages and Sizing Optimization, D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Tompson, K. Keutzer, International Symposium on Low Power Electronics and Design, 158-163, August, 2003
• Methods for Evaluating and Covering the Design Space during Early Design Development, Matthias Gries, Electronics Research Lab, University of California at Berkeley, UCB/ERL M03/32, August, 2003
• Performance Analysis of the Peripheral-Processor Interaction in Embedded Systems, Christian Sauer, Matthias Gries, Chidamber Kulkarni, Kurt Keutzer, Electronics Research Lab, University of California at Berkeley, UCB/ERL M03/26, June, 2003
• Closing the Speed Gap between ASIC and Custom, David Chinnery, Kurt Keutzer, June, 2003
• The Liberty Simulation Environment as a Pedagogical Tool, Jason Blome, Manish Vachharajani, Neil Vachharajani, David August, Proceedings of the Workshop on Computer Architecture Education, June, 2003
• Automated Synthesis of Efficient Binary Decoders for Retargetable Software Toolkits, Wei Qin, Sharad Malik, DAC'03, June, 2003
• Multi-View Operation-Level Design -- Supporting the Design of Irregular ASIPS, Scott Weber, Matthew W. Moskewicz, Manuel Loew, Kurt Keutzer, University of California, Berkeley, UCB/ERL M03/12, April, 2003
• Comparing Analytical Modeling with Simulation for Network Processors: A Case Study, Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer, Design, Automation, and Test in Europe (DATE), Munich, Germany, 256-261, March, 2003
• Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation, Wei Qin, Sharad Malik, Design, Automation, and Test in Europe (DATE), March, 2003
• Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors, Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer, 2nd Workshop on Network Processors (NP2) at the 9th International Symposium on High Performance Computer Architecture (HPCA9), Anaheim CA, 75-87, February, 2003
• NP-Click: A Programming Model for the Intel IXP1200, Niraj Shah, William Plishker, Kurt Keutzer, 2nd Workshop on Network Processors (NP-2) at the 9th International Symposium on High Performance Computer Architecture (HPCA-9), Anaheim, CA, February, 2003
• Mapping Concurrent Applications onto Architectural Platforms, Andrew Mihal, Kurt Keutzer, A. Jantsch, H. Tenhunen, 3, 39-59, Kluwer Academic Publishers, 2003
• Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors, In: Network Processor Design: Issues and Practices, volume 2, Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer, M. Franklin, P. Crowley, H. Hadimioglu, P. Onufryk, 7, 133-158, 2, Morgan Kaufmann Publishers, 2003
• Network Processors: Origin of Species, Niraj Shah, Kurt Keutzer, Proceedings of ISCIS XVII, The Seventeenth International Symposium on Computer and Information Sciences, October, 2002
• Design Tools for Application Specific Embedded Processors, Wei Qin, S. Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh, EMSOFT '02, October, 2002
• CLICK Application Development, Andrew Mihal, 4, September, 2002
• Mapping Applications onto Architectures, Andrew Mihal, 6, June, 2002
• Exploiting Operation Level Parallelism through Dynamically Reconfigurable Datapaths, Zhining Huang, Sharad Malik, Design Automation Conference, June, 2002
• A Benchmarking Methodology for Network Processors, Melvin Tsai, Chidamber Kulkarni, Christian Sauer, Niraj Shah, Kurt Keutzer, 1st Workshop on network processors along with HPCA 2002, February, 2002
• From ASIC to ASIP: The Next Design Discontinuity, Kurt Keutzer, Sharad Malik, Richard Newton, ICCD, January, 2002
• Datapath Merging and Interconnect Sharing for Reconfigurable Architectures, N. Moreano, G. Araujo, Z. Huang, S. Malik, ISSS, January, 2002
• Developing Architectural Platforms: A Disciplined Approach, Andrew Mihal, Chidamber Kulkarni, Christian Sauer, Kees Vissers, Matthew W. Moskewicz, Melvin Tsai, Niraj Shah, Scott Weber, Yujia Jin, Kurt Keutzer, Sharad Malik, 6-16, 19, IEEE Design and Test of Computers, 2002
• Closing the Gap between ASIC and Custom: Tools and Techniques for High-Performance ASIC Design, David Chinnery, Kurt Keutzer, Kluwer Academic Publishers (now Springer), 2002, 1-4020-7113-2
• A Benchmarking Methodology for Network Processors, Network Processors Design: Issues and Practices, Melvin Tsai, Chidamber Kulkarni, Christian Sauer, Niraj Shah, Kurt Keutzer, Patrick Crowley, Mark Franklin, Haldun Hadmioglu, Peter Onufryk, 7, 1, Morgan Kaufmann Publishers, 2002
• Accelerating Boolean Satisfiability through Application Specific Processing, Y. Zhao, M. W. Moskewicz, C. Madigan, S. Malik, Proceedings of the International Symposium on System Synthesis (ISSS), IEEE, October, 2001
• A Brief Tutorial on Models of Computation, Kurt Keutzer, Matthias Gries, Christian Sauer, Kees Vissers, Yujia Jin, Andrew Mihal, Matthew W. Moskewicz, William Plishker, Kaushik Ravindran, Niraj Shah, Scott Weber, 8, September, 2001
• A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage, Serdar Tasiran, Farzan Fallah, David Chinnery, Scott Weber, Kurt Keutzer, International Conference on Computer Design, 82-88, September, 2001
• Achieving 550 MHz in an ASIC Methodology, David Chinnery, Borivoje Nikolic, Kurt Keutzer, Design Automation Conference, 420-425, June, 2001
• Coverage-Directed Generation of Biased Random Inputs for Functional Validation of Sequential Circuits, S. Tasiran, F. Fallah, D. Chinnery, S. Weber, K. Keutzer, International Workshop on Logic and Synthesis, 287-292, June, 2001
• Networks: Present and Future, David Chinnery, Michael Shilman, Melvin Tsai, March, 2001
• A Disciplined Approach to the Development of Platform Architectures, David August, Kurt Keutzer, Sharad Malik, Richard Newton, SASIMI, January, 2001
• Matching Architecture to Application via Configurable Processors: A Case Study with the Boolean Satisfiability Problem, Y. Zhao, A. Wang, M. W. Moskewicz, C. Madigan, S. Malik, ICCD, January, 2001
• Closing the Gap Between ASIC and Custom: An ASIC Perspective, David Chinnery, Kurt Keutzer, Design Automation Conference, 637-642, June, 2000

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