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MESCAL Research Laboratory
Stretch Lab
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| Stretch S56DB10 |
The Stretch platform consists of an Xtensa processor tightly coupled with a fabric that holds instructions that are to be accelerated. This results in a processor-copressor system with high computational power. The fabric can be programmed using a language called Stretch C for which compilation tools are provided as part of the Stretch platform.
In the Stretch lab, we use the Stretch board to test a design flow from Matlab to the Stretch part. We received the Stretch
S56DB10 platform as a donation from Stretch Incorporated. This platform
consists of a Stretch S5610 processor, 256 MB of DDR SDRAM, a RS232
port
for debugging and JTAG/ethernet interfaces for programming/debugging.
The S5610 processor consists of a Tensilica Xtensa processor and a
customized Instruction Set Extension Fabric (ISEF). The programming
environment is a mixture of C for the Xtensa and Stretch C, which is a
variant of C designed for describing instruction extensions. The
platform also comes with software tools that are integrated into the
Stretch Integrated Development Environment (IDE). These include a
compiler flow from Stretch C, a debugger and profiler. Currently, a
number of DSP kernels have been tried out on the board. We propose to
use the board for implementing JPEG and H.264 applications.
Network Processor Lab
In the Network Processor Lab, we
test our methodologies and tools on the
latest commercial network processors. We have received a generous
donation from Intel of 2 Radysis
ENP2611 boards and workstations to put
them in. Each one has 3 Gigabit Ethernet Fiber Ports, 64MB of SDRAM,
4MB
of SRAM over 2 channels, and a 600MHz IXP2400
network processor from
Intel. Representative of the IXP2xxx series, the IXP2400 sports 8
processing elements tailored to packet processing (called
MicroEngines),
an XScale, a hash engine, and over 24 on-chip, distributed memories.
The
architecture's custom hardware and topology tuned for packet processing
affords it high performance (it targets OC-48 line rates), while its
programmability allows it to remain flexible enough to support a
variety
of networking applications. Currently, we are targeting this
architecture with IPv4 forwarding, network address translation, and web
switching based on payload inspection.
Soft Multiprocessor Lab
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| Xilinx ML-310 |
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Xilinx XUP |
A soft multiprocessor system is a network of programmable processors crafted out of processing elements, logic blocks and memories on an FPGA. They allow the user to customize the number of programmable processors, interconnect schemes, memory layout and peripheral support to meet application needs. Deploying an application on the FPGA is tantamount to writing software for this multiprocessor system.
In this lab, we deploy soft multiprocessor designs on the Xilinx Virtex-II family of FPGAs. The Xilinx Embedded Development Kit (EDK) environment provides the tools and libraries to integrate the IBM PowerPC 405 cores on chip, soft MicroBlaze cores, IBM CoreConnect buses and customizable peripherals to design multiprocessor micro-architectures. We use two platforms to demonstrate our designs. The Xilinx ML-310 FPGA development platform has a Virtex-II Pro XC2VP30 FPGA, 256 MB DDR RAM, 512 MB CompactFlash card, 4 PCI slots, 10/100 Ethernet NIC and an AC-97 audio codec. The 2VP30 FPGA consists of 13,696 slices, 136 BlockRAM modules (each BRAM module is 18 Kbits), 136 18x18 multipliers and 2 embedded PowerPC 405 processors. The Xilinx XUP Virtex-II Pro development system has a XC2VP30 FPGA and 256 MB DDR SDRAM. Additionally four Multi-Gigabit transceivers (MGTs) in the FPGA are brought out to SATA and SMA connectors on the board. The XUP also has optical gigabit ethernet extension cards to provide high speed network interfaces.
Our current focus is to deploy high performance network applications on these platforms. We study soft multiprocessor designs for IPv4 packet forwarding, Network Address Translation and the DSL Access Multiplexer (DSLAM) application benchmarks. We specify the applications in Click, a domain specific language for network applications. To systematically explore the design space of soft multiprocessors for a target application, we also develop an automated exploration framework to determine efficient micro-architectures, task allocations and data layouts.
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