A Time-Predictable DRAM Controller for Mixed Time-Criticality Systems
Hokeun Kim, Daniel Oh, Edward A. Lee

Citation
Hokeun Kim, Daniel Oh, Edward A. Lee. "A Time-Predictable DRAM Controller for Mixed Time-Criticality Systems". Talk or presentation, 13, February, 2014; Poster presented at the 2014 Berkeley EECS Annual Research Symposium.

Abstract
Mixed time-criticality systems, where tasks with different levels of timing constraints are running on the same hardware platform, introduce new challenges. To address those challenges, we propose a specialized DRAM memory controller that guarantees significantly lower worst-case latency and higher worst-case bandwidth for hard real-time tasks than traditional DRAM controllers while providing best effort performance for non hard real-time tasks. This is realized by bank-aware division of physical memory space of DRAM and prioritization of memory requests to reserved memory space. The proposed controller is evaluated by replaying memory traces obtained from executing benchmarks on RISC-V Rocket processor. A subset of RISC-V C benchmarks is selected with the size of their data sets increased, to assess DRAM performance under high memory contention. For even higher memory intensiveness and bandwidth measurements, two of the benchmarks are modified to include direct memory access (DMA) requests. Although still preliminary, the evaluation results show that up to 83.0% lower worst-case latency and 117% higher worst-case bandwidth for hard real-time tasks are achieved at cost of slightly higher average latency and lower average bandwidth for non-hard real-time tasks, compared to traditional DRAM scheduling policies.

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Citation formats

• HTML

  Hokeun Kim, Daniel Oh, Edward A. Lee. <a
  href="http://www.terraswarm.org/pubs/266.html"><i>A
  Time-Predictable DRAM Controller for Mixed Time-Criticality
  Systems</i></a>, Talk or presentation,  13,
  February, 2014; Poster presented at the <a
  href="http://www.terraswarm.org/conferences/14/bears/index.htm"
  >2014 Berkeley EECS Annual Research Symposium</a>.

• Plain text

  Hokeun Kim, Daniel Oh, Edward A. Lee. "A
  Time-Predictable DRAM Controller for Mixed Time-Criticality
  Systems". Talk or presentation,  13, February, 2014;
  Poster presented at the <a
  href="http://www.terraswarm.org/conferences/14/bears/index.htm"
  >2014 Berkeley EECS Annual Research Symposium</a>.

• BibTeX

  @presentation{KimOhLee14_TimePredictableDRAMControllerForMixedTimeCriticality,
      author = {Hokeun Kim and Daniel Oh and Edward A. Lee},
      title = {A Time-Predictable DRAM Controller for Mixed
                Time-Criticality Systems},
      day = {13},
      month = {February},
      year = {2014},
      note = {Poster presented at the <a
                href="http://www.terraswarm.org/conferences/14/bears/index.htm"
                >2014 Berkeley EECS Annual Research Symposium</a>.},
      abstract = {Mixed time-criticality systems, where tasks with
                different levels of timing constraints are running
                on the same hardware platform, introduce new
                challenges. To address those challenges, we
                propose a specialized DRAM memory controller that
                guarantees significantly lower worst-case latency
                and higher worst-case bandwidth for hard real-time
                tasks than traditional DRAM controllers while
                providing best effort performance for non hard
                real-time tasks. This is realized by bank-aware
                division of physical memory space of DRAM and
                prioritization of memory requests to reserved
                memory space. The proposed controller is evaluated
                by replaying memory traces obtained from executing
                benchmarks on RISC-V Rocket processor. A subset of
                RISC-V C benchmarks is selected with the size of
                their data sets increased, to assess DRAM
                performance under high memory contention. For even
                higher memory intensiveness and bandwidth
                measurements, two of the benchmarks are modified
                to include direct memory access (DMA) requests.
                Although still preliminary, the evaluation results
                show that up to 83.0% lower worst-case latency and
                117% higher worst-case bandwidth for hard
                real-time tasks are achieved at cost of slightly
                higher average latency and lower average bandwidth
                for non-hard real-time tasks, compared to
                traditional DRAM scheduling policies.},
      URL = {http://terraswarm.org/pubs/266.html}
  }
  

Posted by Hokeun Kim on 18 Feb 2014.
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