Low-Voltage Low-Overhead Asynchronous Logic
Akshay Sridharan, Carl Sechen, Roozbeh Jafari

Citation
Akshay Sridharan, Carl Sechen, Roozbeh Jafari. "Low-Voltage Low-Overhead Asynchronous Logic". Proceedings of International Symposium on Low Power Electronics and Design 2013, September, 2013.

Abstract
A new delay-bounded asynchronous logic technique aimed at maximizing reliability at very low voltages is proposed. Compared to previous asynchronous logic approaches, the area and nominal delay overheads are small. Conventional standard cell libraries and conventional logic synthesis tools are used. The bounding delay elements used by the asynchronous controller feature programmable delays that are initially set based on static timing analysis. However, the delay elements are updated on-the-fly during actual operation of the circuit, resulting in strong resiliency even at low voltages and with extreme variations. Several benchmark circuits were implemented with the new asynchronous design flow using the 45nm TI process. Monte Carlo analysis demonstrates the expected resiliency. Compared to the equivalent synchronous circuits, the asynchronous versions have area overheads averaging 40%, although much smaller for large circuits. Nominal delay overheads average about 10%.

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Citation formats

• HTML

  Akshay Sridharan, Carl Sechen, Roozbeh Jafari. <a
  href="http://www.terraswarm.org/pubs/67.html"
  >Low-Voltage Low-Overhead Asynchronous Logic</a>,
  Proceedings of International Symposium on Low Power
  Electronics and Design 2013, September, 2013.

• Plain text

  Akshay Sridharan, Carl Sechen, Roozbeh Jafari.
  "Low-Voltage Low-Overhead Asynchronous Logic".
  Proceedings of International Symposium on Low Power
  Electronics and Design 2013, September, 2013.

• BibTeX

  @inproceedings{SridharanSechenJafari13_LowVoltageLowOverheadAsynchronousLogic,
      author = {Akshay Sridharan and Carl Sechen and Roozbeh Jafari},
      title = {Low-Voltage Low-Overhead Asynchronous Logic},
      booktitle = {Proceedings of International Symposium on Low
                Power Electronics and Design 2013},
      month = {September},
      year = {2013},
      abstract = {A new delay-bounded asynchronous logic technique
                aimed at maximizing reliability at very low
                voltages is proposed. Compared to previous
                asynchronous logic approaches, the area and
                nominal delay overheads are small. Conventional
                standard cell libraries and conventional logic
                synthesis tools are used. The bounding delay
                elements used by the asynchronous controller
                feature programmable delays that are initially set
                based on static timing analysis. However, the
                delay elements are updated on-the-fly during
                actual operation of the circuit, resulting in
                strong resiliency even at low voltages and with
                extreme variations. Several benchmark circuits
                were implemented with the new asynchronous design
                flow using the 45nm TI process. Monte Carlo
                analysis demonstrates the expected resiliency.
                Compared to the equivalent synchronous circuits,
                the asynchronous versions have area overheads
                averaging 40%, although much smaller for large
                circuits. Nominal delay overheads average about
                10%.},
      URL = {http://terraswarm.org/pubs/67.html}
  }
  

Posted by Mila MacBain on 14 May 2013.