Package ptolemy.actor.lib.vhdl

VHSIC Hardware Description Language (VHDL) actors.

See: Description

Class Summary

Class	Description
AddSubtract	Produce an output token on each firing with a FixPoint value that is equal to the sum of all the inputs at the plus port minus the inputs at the minus port.
Concat	Produce an output token on each firing with a FixPoint value that is equal to the concatenation of the input bits from each input channel.
FixComparator	Produce an output token on each firing with a FixPoint value that is equal to the sum of all the inputs at the plus port minus the inputs at the minus port.
FixConst	Produce a fix point constant output.
FixCounter	A class for a fixpoint value counter.
FixSequence	This actor produces a sequence of values, optionally periodically repeating them.
FixToString	Produce an output token on each firing with a FixPoint value that is equal to the slicing of the bits of the input token value.
FixTransformer	This is an abstract base class for actors that transform an input stream into output stream.
IntegerCounter	A class for a integer counter.
LogicalNot	Produce an output token on each firing with a FixPoint value that is equal to the sum of all the inputs at the plus port minus the inputs at the minus port.
LogicFunction	Produce an output token on each firing with a FixPoint value that is equal to the sum of all the inputs at the plus port minus the inputs at the minus port.
Memory	Produce an output token on each firing with a FixPoint value that is equal to the concatenation of the input bits from each input channel.
Multiplexor	Produce an output token on each firing with a FixPoint value that is equal to the slicing of the bits of the input token value.
Multiplier	Produce an output token on each firing with a FixPoint value that is equal to the sum of all the inputs at the plus port minus the inputs at the minus port.
QueuedTypedIOPort	Delays each fixed point token sent on the port by the specified latency parameter and then outputs it via the parent TypedIOPort.
Register	A register is a stateful actor with a trigger port that accepts read requests.
RegisterSR	This actor provides a one-tick delay.
ROM	Produce an output token on each firing with a FixPoint value that is equal to the concatenation of the input bits from each input channel.
Slice	Produce an output token on each firing with a FixPoint value that is equal to the slicing of the bits of the input token value.
SynchronousFixTransformer	This is an abstract base class for actors that transform an input stream into an output stream with a specified latency parameter.

Package ptolemy.actor.lib.vhdl Description

VHSIC Hardware Description Language (VHDL) actors. VHDL is a language that is used to program hardware such as Field Programmable Gate Arrays (FPGAs). These actors are usually used in conjunction with the VHDL code generator.

Since:

Ptolemy II 6.1