Chapter 4. Introduction to Domains, Targets, and Foreign Tool Interfaces

• 4.1 Introduction

• 4.2 Synchronous dataflow (SDF)

• 4.3 Higher-Order Functions (HOF)

• 4.4 Dynamic dataflow (DDF)

• 4.5 Boolean dataflow (BDF)

• 4.6 Process Network (PN)

• 4.7 Synchronous Reactive (SR)

• 4.8 Finite State Machine (FSM)

• 4.9 Discrete Event (DE)

• 4.10 Multidimensional Synchronous Dataflow (MDSDF)

• 4.11 Code generation (CG)

• 4.12 Code generation in C (CGC)

• 4.13 Code generation for the Motorola DSP56000 (CG56)

• 4.14 Code generation in VHDL (VHDL, VHDLB)

• 4.15 Domains that have been removed
  • 4.15.1 Circuit simulation (Thor)
  • 4.15.2 Communicating processes (CP)
  • 4.15.3 Message queueing (MQ)
  • 4.15.4 Code generation for the Sproc multiprocessor DSP (Sproc)
  • 4.15.5 Code generation for the Motorola DSP96000 (CG96)
  • 4.15.6 Code generation in Silage (Silage)
  • 4.15.7 Functional Code Generation in VHDL (VHDLF)

• 4.16 Interfaces to Foreign Tools
  • 4.16.1 Specification and Layout
  • 4.16.2 Parameter Calculation
  • 4.16.3 Algorithm Prototyping and Visualization
  • 4.16.4 Simulation
  • 4.16.5 Synthesis

Authors: Joseph T. Buck
Brian L. Evans
Soonhoi Ha
Asawaree Kalavade
Edward A. Lee
Thomas M. Parks

Michael C. Williamson

Other Contributors: The entire Ptolemy team