Architectures for statically scheduled dataflow

Edward A. Lee and Jeffery C. Bier

Journal of Parallel Distributed Computing, pp. 333-348, Vol. 10, Issue 4, December, 1990.


When dataflow program graphs can be statically scheduled, little run-time overhead (software or hardware) is necessary. This paper describes a class of parallel architectures consisting of von Neumann processors and one or more shared memories, where the order of shared-memory accesses is determined at compile time and enforced at run time. The architecture is extremely lean in hardware, yet for a set of important applications it can perform as well as any shared-memory architecture. Dataflow graphs can be mapped onto it statically. Furthermore, it supports shared data structures without the run-time overhead of I-structures. A software environment has been constructed that automatically maps signal processing applications onto a simulation of such an architecture, where the architecture is implemented using Motorola DSP96002 microcomputers. Static (compile-time) scheduling is possible for a subclass of dataflow program graphs where the firing pattern of actors is data independent. This model is suitable for digital signal processing and some other scientific computation. It supports recurrences, manifest iteration, and conditional assignment. However, it does not support true recursion, data-dependent iteration, or conditional evaluation. An effort is under way to weaken the constraints of the model to determine the implications for hardware design.