Optimized Software Synthesis for Synchronous Dataflow

Shuvra S. Bhattacharyya, Hitachi America
Praveen K. Murthy, University of California at Berkeley
Edward A. Lee, University of California at Berkeley

Intl. Conf. on Application-specific Systems, Architectures & Processors, July, 1997, invited paper

Prepublished version
Published version


This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded signal processing applications into efficient implementations on programmable digital signal processors. This is a critical problem because programmable digital signal processors have very limited amounts of on-chip memory, and the speed and power penalties for using off-chip memory are often prohibitively high for the types of applications, typically embedded systems, where these processors are used. Moreover, off-chip memory typically needs to be static, increasing the system cost considerably.

The compiling techniques described in the paper are developed for the synchronous dataflow model of computation, a model that has found widespread use for specify ing and prototyping DSP systems.

Send comments to Shuvra S. Bhattacharyya at shuvra at hmsi hitachi com .