Introduction
People Research
themes: Embedded Systems
Hybrid Systems
Deep Submicron
Logic Synthesis
Other links:
EE249
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GSRC
BWRC

Logic Synthesis
Publications:
S.
Khatri, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Crosstalk Immune VLSI Design Using Regular
Layout Fabrics. Kluwer Academic Publishers, 2001.
M.
D. Di Benedetto, A.
L. SangiovanniVincentelli, and T.
Villa. Model Matching for Finite State Machines. IEEE Transactions on
Automatic Control, 46(11):17261743, November 2001.
N.
Yevtushenko, T.
Villa, R.
K. Brayton, A.
Petrenko, and A.
L. SangiovanniVincentelli. Solution of Parallel Language Equations for
Logic Synthesis. In The Proceedings of the International Conference on
Computer Aided Design, pages 103110, November 2001.
L.
Lavagno, T.
Villa, and A.
L. SangiovanniVincentelli. Advances in Encoding for Logic Synthesis. In G.
W. Zobrist, editor, VLSI Design Environments. Gordon and Breach Science
Publishers, 2000.
A.
Aziz, F.
Balarin, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Sequential synthesis using S1S. IEEE
Transactions on ComputerAided Design, 19(10):11491162, October 2000.
E.I. Goldberg, L.P. Carloni, T. Villa, R. K. Brayton and
A.L. SangiovanniVincentelli, Negative Thinking in BranchandBound: the Case of Unate
Covering,
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 19, No. 3, March 2000.
L.P. Carloni, E.I. Goldberg, T. Villa, R.K. Brayton and
A.L. SangiovanniVincentelli, Aura II: Combining Negative Thinking and BranchandBound in Unate Covering
Problems,
In "VLSI: Systems on a Chip" (L.M. Silveira, R. Reis, S. Devadas editors), Kluwer 1999.
A.L. Oliveira,
L.P. Carloni, T. Villa and A.L. SangiovanniVincentelli, Exact
Minimization of Binary Decision Diagrams Using Implicit Techniques, IEEE
Transactions on Computers, Vol. 47, No. 11, November 1998.
E.
Goldberg, T.
Villa, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Theory and Algorithms for Face Hypercube
Embedding. IEEE Transactions on ComputerAided Design, 17(6):472488,
June 1998.
T.
Kam, T.
Villa, R.
K. Brayton, and A.
L. SangiovanniVincentelli. MultiValued Decision Diagrams: Theory and
Applications. International Journal on MultipleValued Logic,
4(12):962, 1998.
W.
Gosti, T.
Villa, A.
Saldanha, and A.
L. SangiovanniVincentelli. An Exact Input Encoding Algorithm for BDDs
Representing FSMs. In Proceedings of the 8th Great Lakes Symposium on VLSI,
pages 294300, February 1998.
A.L. Oliveira, L.P.
Carloni, T. Villa and A.L. SangiovanniVincentelli,
Exact Minimization of Binary Decision Diagrams Using Implicit Techniques,
IEEE Transactions on Computers, Vol. 47, No. 11, November 1998.
T.
Kam, T.
Villa, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Synthesis of FSMs: Functional Optimization.
Kluwer Academic Publishers, 1997.
T.
Villa, T.
Kam, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Synthesis of FSMs: Logic Optimization. Kluwer
Academic Publishers, 1997.
T. Kam, T.
Villa, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Implicit Computation of Compatible Sets for
State Minimization of ISFSMs. IEEE Transactions on ComputerAided Design,
16(7):657676, July 1997.
T.
Kam, T.
Villa, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Theory and Algorithms for State Minimization of
Nondeterministic FSMs. IEEE Transactions on ComputerAided Design,
16(11):13111322, November 1997.
T.
Villa, T.
Kam, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Explicit and Implicit Algorithms for Binate
Covering Problems. IEEE Transactions on ComputerAided Design,
16(7):677691, July 1997.
T.
Villa, A.
Saldanha, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Symbolic TwoLevel Minimization. IEEE
Transactions on ComputerAided Design, 16(7):692708, July 1997.
P. Buch, A.
Narayan, R.
Newton, and A.
L. SangiovanniVincentelli. Logic Synthesis for Large Pass Transistor
Circuits. In The Proceedings of the International Conference on
ComputerAided Design, pages 663670, November 1997.
L.
P. Carloni, P.
McGeer, A.
Saldanha, and A.
L. SangiovanniVincentelli. TraceDriven Logic Synthesis: Application to
Power Minimization. In The Proceedings of the International Conference on
ComputerAided Design, pages 581588, November 1997.
A.
L. Oliveira, L. P. Carloni, T.
Villa, and A.
L. SangiovanniVincentelli. An Implicit Formulation for Exact BDD
Minimization of Incompletely Specified Functions. In Ricardo Reis and Luc
Claesen, editors, VLSI: Integrated Systems on Silicon, Proceedings of VLSI
'97, Gramado, Brazil, pages 315326, August 1997. ChapmanHall.
E.I. Goldberg, L.P. Carloni, T. Villa, R.K. Brayton and
A.L. SangiovanniVincentelli, Negative Thinking in Search Methods: Application to Unate
Covering,
The Proceedings of the International Conference on ComputerAided Design, 1997.
W.
Lam, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Valid Clock Frequencies and Their Computation in
Wavepipelined Circuits. IEEE Transactions on ComputerAided Design,
15(7):791807, July 1996.
A.
L. Oliveira and A.
L. SangiovanniVincentelli. Using the Minimum Description Length Principle
to Infer Reduced Ordered Decision Graphs. Machine Learning, 25(1):2350,
October 1996. Kluwer Academic Publishers.
P.
Stephan, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Combinational Test Generation Using
Satisfiability. IEEE Transactions on ComputerAided Design,
15(9):11671176, September 1996.
R.
K. Brayton, G.
Hachtel, A.
L. SangiovanniVincentelli, F.
Somenzi, A.
Aziz, S.T.
Cheng, S.
Edwards, S.
Khatri, Y.
Kukimoto, A.
Pardo, S.
Qadeer, R.
Ranjan, S.
Sarwary, T.
Shiple, G.
Swamy, and T.
Villa. VIS: A System for Verification and Synthesis. In R. Alur and T.
Henzinger, editors, The Proceedings of the Conf. on ComputerAided
Verification, volume 1102 of LNCS, pages 332334, August 1996.
Springer Verlag.
R.
K. Brayton, G.
Hachtel, A.
L. SangiovanniVincentelli, F.
Somenzi, A.
Aziz, S.T.
Cheng, S.
Edwards, S.
Khatri, Y.
Kukimoto, A.
Pardo, S.
Qadeer, R.
Ranjan, S.
Sarwary, T.
Shiple, G.
Swamy, and T.
Villa. VIS. In M. Srivas and A. Camilleri, editors, Proc. of the Conf.
on Formal Methods in ComputerAided Design, volume 1166 of LNCS,
pages 248256, November 1996. Springer Verlag.
T.
Shiple, V.
Singhal, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Analysis of Combinational Cycles in Sequential
Circuits. In The Proceedings of the International Symposium on Circuits and
Systems, pages 592595, vol. IV, May 1996.
R.
Murgai, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Logic Synthesis for FieldProgrammable Gate
Arrays. Kluwer Academic Publishers, 1995.
W.
Lam, A.
Saldanha, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Delay Fault Coverage, Test Set Size, and
Performance Tradeoffs. IEEE Transactions on ComputerAided Design,
14(1):3244, January 1995.
P.C.
McGeer, K.L.
McMillan, A.
Saldanha, A.
L. SangiovanniVincentelli, and P.
Scaglia. Fast discrete function evaluation using decision diagrams. In The
Proceedings of the International Conference on ComputerAided Design, pages
402407, November 1995.
A.
Saldanha, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Circuit Structure Relations to Redundancy and
Delay. IEEE Transactions on ComputerAided Design, 13(7):875883, July
1994.
A.
Saldanha, T.
Villa, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Satisfaction of Input and Output Encoding
Constraints. IEEE Transactions on ComputerAided Design, 13(5):589602,
May 1994.
A.
Malik, R.
K. Brayton, R.
Newton, and A.
L. SangiovanniVincentelli. TwoLevel Minimization of Multivalued Functions
with Large Offsets. IEEE Transactions on ComputerAided Design,
42(11):13251342, November 1993.
S.
Malik, K.
J. Singh, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Performance Optimization of Pipelined Logic
Circuits Using Peripheral Retiming and Resynthesis. IEEE Transactions on
ComputerAided Design, 12(5):568578, May 1993.
P.
McGeer, J.
Sanghavi, R.
K. Brayton, and A.
L. SangiovanniVincentelli. ESPRESSOSIGNATURE: a New Exact Minimizer for
Logic Functions. IEEE Transactions on VLSI Systems, 1(4):432440,
December 1993.
A.
L. Oliveira and A. L. SangiovanniVincentelli. Learning Complex Boolean Functions : Algorithms
and Applications. In Advances in Neural Information Processing Systems 6,
Denver, CO, pages 911918, 1993. Morgan Kaufmann.
N.
Shenoy, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Resynthesis of MultiPhase Pipelines. In The
Proceedings of the 30th ACM/IEEE Design Automation Conference, pages
490496, June 1993.
P.
McGeer, A.
Saldanha, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Delay Models and Exact Timing Analysis. In T.
Sasao, editor, New Trends in Logic Synthesis and Optimization. Kluwer,
1992.
S.
Malik, L.
Lavagno, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Symbolic Minimization of Multilevel Logic and
the Input Encoding Problem. IEEE Transactions on ComputerAided Design,
11(7):825843, July 1992.
A.
L. Oliveira and A.
L. SangiovanniVincentelli. Constructive Induction Using a NonGreedy
Strategy for Feature Selection. In Proceedings of the Ninth
International
Conference in Machine Learning, Aberdeen, Scotland, pages 355360, 1992.
Morgan Kaufmann.
N.
Shenoy, K.
J. Singh, R.
K. Brayton, and A.
L. SangiovanniVincentelli. On the Temporal Equivalence of Sequential
Circuits. In The Proceedings of the 29th ACM/IEEE Design Automation
Conference, pages 405409, June 1992.
A.
Malik, R.
K. Brayton, R.
Newton, and A.
L. SangiovanniVincentelli. Reduced Offsets for Minimization of
BinaryValued Functions. 10(4):413426, April 1991.
S.
Malik, E.
M. Sentovich, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Retiming and Resynthesis: Optimizing Sequential
Circuits Using Combinational Techniques. 10(1):7484, January 1991.
A.
L. Oliveira and A.
L. SangiovanniVincentelli. Learning Concepts by Synthesizing Minimal
Threshold Gate Networks. In L. Birnbaum and G. C. Collins, editors, Proceedings
of the Eigth International Workshop in Machine Learning, Chicago, IL, pages
193197, 1991. Morgan Kaufmann.
A.
L. Oliveira and A.
L. SangiovanniVincentelli. LSAT  An Algorithm for the Synthesis of Two
Level Threshold Gate Networks. In The Proceedings of the International
Conference on ComputerAided Design, Santa Clara, CA, pages 130133, 1991.
IEEE Computer Society Press.
N.
Shenoy, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Retiming of Circuits with Single Phase
Transparent Latches. In The Proceedings of the International Conference on
Computer Design, pages 8689, October 1991.
R. K. Brayton, A.
L. SangiovanniVincentelli, and G. Hachtel. Multilevel logic synthesis. Proceedings
of the IEEE, vol. 78(no. 2):264300, February 1990.
T.
Villa and A.
L. SangiovanniVincentelli. NOVA: State Assignment for Optimal TwoLevel
Logic Implementations. IEEE Transactions on ComputerAided Design,
9(9):905924, September 1990.
S.
Devadas, A.
Wang, R.
Newton, and A.
L. SangiovanniVincentelli. Boolean Decomposition in Multilevel Logic
Optimization. IEEE Journal of solidstate circuits, pp 399408, April
1989.
K.
Bartlett, R.
K. Brayton, G. Hachtel, R.
Jacoby, C.
Morrison, R.
Rudell, A.
L. SangiovanniVincentelli, and A.
Wang. Multilevel Logic Minimization using Implicit Don't Cares. transcad,
June 1988.
R.
K. Brayton, R.
Rudell, A.
L. SangiovanniVincentelli, and A.
Wang. MIS: A MultipleLevel Logic Optimization System. IEEE Transactions
on ComputerAided Design, pp 10621081, November 1987.
R.
Rudell and A.
L. SangiovanniVincentelli. MultipleValued Minimization for PLA
Optimization. IEEE Transactions on ComputerAided Design, CAD6:727750,
September 1987.
G.
De Micheli, R.
K. Brayton, and A.
L. SangiovanniVincentelli. Optimal State Assignment for Finite State
Machines. IEEE Transactions on ComputerAided Design, CAD4:269285, July
1985.
R.
K. Brayton, G.
Hachtel, C.
McMullen, and A.
L. SangiovanniVincentelli. Logic Minimization Algorithms for VLSI
Synthesis. Kluwer Academic Publishers, 1984.
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