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16.4 An Overview of VHDL Demos

The figure below shows the top-level palette of VHDL demos. The demos are divided into categories: code generation, simulation, synthesis, and cosimulation. Some of the demos in the VHDL domain have equivalent counterparts in the SDF or CGC domains. See "An overview of SDF demonstrations" on page 5-51 for brief descriptions of these demos. Brief descriptions of the demos unique to the VHDL domain are given in the sections that follow.

FIGURE 16-9: Top-level palette of demos in the VHDL domain.

16.4.1 Code Generation Demos

Figures below show demos that do nothing but
generate code.

The sequential demos use the default-VHDL target. The structural demos use the struct-VHDL target. They are essentially the same systems being run, but with two different targets producing two different styles of VHDL code. These demos provide a direct comparison of these two basic styles of VHDL code generation.

16.4.2 Simulation Demos

FIGURE 16-12: Demos using the Synopsys VSS Simulator.

These demos use the SimVSS-VHDL target. Each one generates VHDL code which is functionally equivalent to the SDF graph specification, and then the code is executed on the Synopsys VSS Simulator. Graphical monitoring blocks provide output analysis of the results of running these systems.

16.4.3 Synthesis Demos

FIGURE 16-13: Demos using the Synopsys Design Analyzer for synthesis.

These demos use the Synth-VHDL target. Each one generates structural VHDL code which is equivalent to the SDF specification. One difference is that the data types are converted to simple 4-bit integers to speed up the synthesis process. Once the code is generated, the netlist is synthesized through the Synopsys Design Analyzer. Following that, the netlist is optimized and then control of the Design Analyzer is returned to the user for further exploration and inspection.

16.4.4 Cosimulation Demos

FIGURE 16-14: Demos mixing simulation in VHDL, C, and Motorola DSP56000 code.

These demos use the CompileCGSubsystems target which uses the SimVSS-VHDL target as a child target for the VHDL portions of the systems. The first three demos generate stand-alone heterogeneous programs which run in C, Motorola DSP56000 assembly, and VHDL. They produce analysis and synthesis filterbanks for perfect reconstruction using progressively more complex structures. The fourth demo also generates a Tcl/Tk user interface for selecting one of three waveform inputs to the system. The fifth and final demo generates the filterbank system, but instead of doing it as a standalone program, it incorporates the system into a wormhole inside a top-level SDF system. This way the subsystem can be executed in code which is potentially faster than SDF simulation, and it can be reused without having to recompile the subsystem each time the top-level system is executed.

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