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16.1 Introduction

The VHDL domain generates code in the VHDL (VHSIC Hardware Description Language) programming language. This domain supports the synchronous dataflow model of computation. This is in contrast to the VHDLB domain, which supports the general discrete-event model of computation of the full VHDL language.

Since the VHDL domain is based on the SDF model, it is independent of any notion of time. The VHDL domain is intended for modeling systems at the functional block level, as in DSP functions for filtering and transforms, or in digital logic functions, independent of implementation issues.

The VHDL domain replaces the VHDLF domain. It is not, however, meant to be used in the same way as the VHDLF domain: the VHDL domain is for generating code from functional block diagrams with SDF semantics, while the VHDLF domain was intended to contrast with the VHDLB domain. It supported structural code generation using VHDL blocks with no execution delay or timing behavior, just functionality. The semantics for the VHDLF domain were not strictly defined, and quite a lot depended on how the underlying VHDL code blocks associated with each VHDLF star were written.

Within the VHDL domain, there are a number of different Targets to choose from. The default target, default-VHDL, generates sequential VHDL code in a single process within a single entity, following the execution order from the SDF scheduler. This code is suitable for efficient simulation, since it does not generate events on signals. The SimVSS-VHDL target is derived from default-VHDL, and provides facilities for simulation using the Synopsys VSS VHDL simulator. Communication actors and facilities in the SimVSS-VHDL target support code synthesis and co-simulation of heterogeneous CG systems under the CompileCGSubsystems target developed by José Pino. There is also a SimMT-VHDL target for use with the Model Technology VHDL simulator. The struct-VHDL target generates VHDL code in which individual actor firings are encapsulated in separate entities connected by VHDL signals. This target generates code which is intended for circuit synthesis. The Synth-VHDL target, derived from struct-VHDL, provides facilities for synthesizing circuit representations from the structural code using the Synopsys Design Analyzer toolset. Each of these targets is discussed in more detail in the next section.

Because the VHDL domain uses SDF semantics, it supports retargeting from other domains with SDF semantics (SDF, CGC, etc.) provided that the stars in the original graph are available in the VHDL domain. As this experimental domain evolves, more options for VHDL code generation from dataflow graphs will be provided. These options will include varying degrees of user control and automation depending on the target and the optimization goals of the code generation, particularly in VHDL circuit synthesis.

16.1.1 Setting Environment Variables

In order to have the Synopsys simulation target work correctly, you should make sure that the following environment variables and paths are set correctly. The SYNOPSYS and
SIM_ARCH shell environment variables are settable within the Synopsys simulation target, SimVSS-VHDL, as target parameters by using edit-target (shift-t).

Also, you may need to permanently add the following lines to your .cshrc file and uncomment the ones you wish to take effect:

# For VHDL Synopsys demos, uncomment the following: 
# setenv SYNOPSYS /usr/tools/synopsys
# setenv SIM_ARCH sparcOS5
# You need the last one of these (.../sge/bin) to run vhdldbx
# since vhdldbx looks for "msgsvr":
# set path = ( $path $SYNOPSYS/$SIM_ARCH/syn/bin $SYNOPSYS/$SIM_ARCH/sim/bin $SYNOPSYS/$SIM_ARCH/sge/bin)
# You need this to run vhdlsim, and since vhdldbx calls vhdlsim, you
# need this to run vhdldbx also:
# For Motorola S56x card demos on the Sparc, you will need something like:
# setenv S56DSP /users/ptdesign/vendors/s56dsp
# setenv QCKMON qckMon5
You will need to have a .synopsys_vss.setup file with the right library directive in it in order to use the communication vhdl modules needed for the CompileCGSubsystems target. This file in the root PTOLEMY directory has the correct directive defining the location of the PTVHDLSIM library. Synopsys simulation only sees the file if it is in one of three places: the current directory in which simulation is invoked, the configuration directory within the Synopsys installation tree, or the user's home directory. Since working directories are frequently created and destroyed, and since the Synopsys installation will vary from site to site, the user's home directory is the best place to put this file, but each user must do this if the root of their personal Ptolemy tree is anything other than their home directory.

Here is the text in $PTOLEMY/.synopsys_vss.setup:

-- This is so communication code can be
-- compiled into the PTVHDLSIM library:
PTVHDLSIM	: $PTOLEMY/obj.$PTARCH/utils/ptvhdlsim

NOTE: If you build your own tree and it includes your own $PTOLEMY/src/utils/ptvhdlsim directory, then you will need to modify your .synopsys_vss.setup file to point to this directory prior to building the new tree. During the build process, this file is needed so that the ptvhdlsim executable can be correctly linked. If it is pointing to some other directory, then you may experience problems linking ptvhdlsim.

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