default-VHDL, struct-VHDL, SimVSS-VHDL, SimMT-VHDL, and Synth-VHDL. There is also support for using SimVSS-VHDL as a child target of CompileCGSubsystems for heterogeneous code generation and co-simulation.All of the VHDL targets share the following parameters, which are inherited from the base class
HLLTarget:
STRING) Default = $HOME/PTOLEMY_SYSTEMS
The name of the directory into which generated code files and supporting files are written. In derived targets, this is also the directory in which compilation for simulation and synthesis are performed.
INT) Default = 0
The control for selecting the looping complexity of the SDF scheduler which is used. Note that looping of code is not supported in the current implementation, except at the main iteration loop on the outside. Therefore a looping level of zero should be used with all loop schedulers or incorrect code may result. In future releases, higher looping levels will be supported.
INT) Default = TRUE
Option to display generated codefiles to the screen.
INT) Default = FALSE
Option to write the schedule to a file. The name of the file will be <galaxy name>.sched.
default-VHDL target generates VHDL code in a simple and straightforward style which is designed to preserve the SDF scheduling order while incurring minimum VHDL simulation overhead. The code is generated as a single VHDL entity containing a single process of sequential statements. The sequential process reflects the order of execution determined by the SDF scheduler. All data values are stored and communicated through internal variables so that the simulation overhead of VHDL signals and the VHDL discrete-event scheduler can be avoided. No actual simulation is performed by the default-VHDL target. It is left to derived targets to support VHDL simulation.To generate the code, the
default-VHDL target first invokes the SDF scheduler, and then goes through the resulting schedule in order, firing each VHDL star in sequence. As each VHDL star is fired, a block of VHDL sequential statements is generated. Porthole and State references and values are resolved and any necessary VHDL variables are created and placed in the list of declared variables. One VHDL star may be fired multiple times and each firing will cause a new codeblock with new variables to be generated. The target manages the communication of data from one VHDL star to the next through VHDL variables. The target also manages state propagation from one firing to the next of the same VHDL star through VHDL variables. State values and tokens remaining on arcs at the end of the schedule iteration are also fed back through the correct variables so that the process can be looped repeatedly and function identically to the original SDF graph.
struct-VHDL target generates VHDL code in a structural style, in which firings of VHDL stars are individually encapsulated in VHDL entities. The entities are connected to one another through VHDL signals, and the flow of data and state from one firing entity to the next enforces the precedence relationships inherent in the dataflow graph and the resulting schedule. The overall structure of the completed code description parallels the precedence directed acyclic graph (DAG).The procedure used by the
struct-VHDL target to generate the code begins similarly to that of the default-VHDL target. First, the SDF scheduler is invoked and a valid schedule is computed. Then the schedule is run, and as each VHDL star is fired, the target generates an individual VHDL entity for each firing while keeping track of input and output references to portholes and states. The target manages the references so that it can correctly instantiate each VHDL entity and create VHDL signals to map to the VHDL ports for carrying data and state from one firing to the next. Only firings which have actual dependencies will be connected in the VHDL code representation. In this way, the code generated represents the maximum parallelism in the graph computation outside the granularity level of an individual firing.The current version of the
struct-VHDL target also generates registers for latching the values of states and remaining tokens at the end of an iteration. It feeds back the outputs of these registers to the correct inputs at the beginning of the graph so that the structure can be "clocked" by an input clock signal common to all such registers. This clock, on a positive transition, represents the tick of one completed iteration of the dataflow graph. This clock becomes an input to the entire top-level VHDL entity, and will presumably be supplied by an outside source or signal driver during simulation. Similarly, there is an input created for a control signal which selects between the initial values of states or initial tokens and the succeeding values which are passed from one iteration to the next.
SimVSS-VHDL target is derived from the default-VHDL target. It generates code in the same single-entity, single-process, sequential style as the default-VHDL target, but it also provides facilities for simulation using the Synopsys VSS VHDL simulator. Depending on the target parameters set when running this target, following the code generation phase this target can compile, elaborate, and execute interactively or non-interactively the design specified by the generated VHDL code.Communication actors and facilities in the
SimVSS-VHDL target support code synthesis and co-simulation of heterogeneous CG systems under the CompileCGSubsystems target developed by José Pino. This allows a user to manually partition a graph using hierarchy so that multiple codefiles of different code generation domains can be generated. They are then executable if run on host machines which provide all the needed simulators and supporting hardware resources that the individual child targets require. The communication between the different code generation subsystems is automatically generated and correct synchronization and deadlock avoidance are guaranteed. This capability is demonstrated with VHDL in a number of demos included through the main VHDL demo palette.The additional parameters of the
SimVSS-VHDL target are as follows:
STRING) Default = /usr/tools/synopsys
Value of the SYNOPSYS environment variable. It points to the root of the Synopsys tools installation on the host machine.
STRING) Default = sparcOS5
Value of the ARCH environment variable. It indicates which architecture/operating system the Synopsys tools will be run on.
STRING) Default = sparcOS5
Value of the SIM_ARCH environment variable. It indicates which architecture/operating system the Synopsys VSS simulator will be run on.
INT) Default = TRUE
If TRUE then attempt to analyze the VHDL code using the gvan tool, checking for syntax errors.
INT) Default = TRUE
If TRUE then attempt to startup the VHDL simulator (vhdldbx if interactive = TRUE, else ptvhdlsim).
INT) Default = TRUE
Currently unused. If interactive = FALSE, simulation under ptvhdlsim will begin automatically following startup.
INT) Default = TRUE
Currently unused.
INT) Default = FALSE
If TRUE then when simulating, run vhdldbx. Otherwise, run ptvhdlsim.
SimMT-VHDL target is derived from the default-VHDL target. It generates code in the same single-entity, single-process, sequential style as the default-VHDL target, and also provides facilities for simulation using the Model Technology VHDL simulator. Depending on the target parameters set when running this target, following the code generation phase this target can compile, elaborate, and execute interactively or non-interactively the design specified by the generated VHDL code.The additional parameters of the
SimMT-VHDL target are as follows:
INT) Default = TRUE
If TRUE then attempt to analyze the VHDL code using the vcom tool, checking for syntax errors.
INT) Default = TRUE
If TRUE then attempt to startup the vsim VHDL simulator
INT) Default = TRUE
Currently unused. If startup = TRUE and interactive = FALSE, simulation under vsim will begin automatically following startup. If startup = TRUE and interactive = TRUE, vsim will startup but wait for user input.
INT) Default = TRUE
Currently unused.
INT) Default = FALSE
If TRUE, then when simulating, start up vsim and wait for user input. If FALSE, then when simulating, run vsim in the background.
Synth-VHDL target is derived from the struct-VHDL target. It generates code in the same structural style as the struct-VHDL target, but it also provides facilities for synthesis and optimization using the Synopsys Design Analyzer toolset.Not every design which can be specified as an SDF graph using the VHDL stars available in the main star palettes will be synthesizable. Some stars generate code which is not synthesizable under the rules required by the Synopsys Design Analyzer.
There is conceptually more than one way to generate synthesizable VHDL for a given dataflow graph. Just as the sequential VHDL of the
default-VHDL target differs from the structural VHDL of the struct-VHDL target, so there are also multiple ways in which the structural VHDL could be generated. The struct-VHDL target as is only generates one particular style. A programmer with some experience could modify this target or create a new or derived target to generate the code in a different structural style to suit different needs. Future releases of Ptolemy may include additional structural VHDL targets for synthesis and/or a modified version of the ones included in the 0.7 release.The additional parameters of the
Synth-VHDL target are as follows:
INT) Default = TRUE
If TRUE then attempt to analyze the VHDL code using the design_analyzer tool, checking for syntax errors.
INT) Default = TRUE
If TRUE then attempt to elaborate the analyzed design into a netlist form.
INT) Default = TRUE
If TRUE then attempt to compile the elaborated design into an optimized netlist.
INT) Default = TRUE
If TRUE then generate reports on the compile-optimized designs for area and timing.
$PTOLEMY/src/domains/vhdl/targets contains the Cadence Leapfrog VHDL Target. This target, SimLF-VHDL, allows simulation of generated VHDL code with the Leapfrog simulator from Cadence. This target is analogous to the SimVSS-VHDL target, which supports simulation with the Synopsys VHDL System Simulator.
/usr/eesww/cadence, so your .cshrc would contain:
setenv PATH /usr/eesww/cadence/9504/tools/leapfrog/bin:$PATHYou also need to set up some files.
setenv CDS_LIB /usr/eesww/cadence/9504/tools/leapfrog
setenv CDS_INST_DIR /usr/eesww/cadence/9504
In the directory where the VHDL code is generated, for example
~/PTOLEMY_SYSTEMS/VHDL, the following two files must be provided:
cds.lib contains
softinclude $CDS_VHDL/files/cds.lib
define leapfrog ./LEAPFROG
define alt_syn $CDS_INST_DIR/lib/alt_syn
hdl.var contains:DEFINE WORK leapfrog include $CDS_VHDL/files/hdl.var
and the directory
~/PTOLEMY_SYSTEMS/VHDL/LEAPFROG must exist