EECS20N: Signals and Systems

Feedback Example 4

In this example, in either state, the output can be determined without knowing the input. The output is again state determined. Thus, the output of this state machine is the sequence

false, false, false, false, false, ...

Notice that the component machine here behaves like a delay. The output is always the previous input, except the first time, where the output is false. Connecting such a delay in this feedback arrangement results in an output that is always false.