Workspaces
----
apbd
asves
asvpapers
bear
blast
caltrop
cases
concurrency
cosi
dif
diva
dopcenter
dopresence
dopsysadmin
eecsx44
elab
embedded
embeddedadmin
giotto
hyinfo
m2t2
mescal
metropolis
mica
mobies
msgadmin
murieh
mvsis
nephest
ransom
recons
robosysadmin
savg
sec
seminar
smartnets
video
webmaster
Note:
JavaScript is disabled
, see the
Site Map
for navigation links
 
Spring 2001 CAD Seminar Schedule
Click on the speaker's name for a brief biography and contact information
Click on the title for a abstract of the talk. If we have electronic copies of transparencies or relevant papers, they can be found here, along with the abstract.
Month
Date
Day
Time
Venue
Speaker
Title
January
17
Wed
5:00 pm
Hogan Room
K.K. Mei
On the differential equations of thin wire structures - Existence, Uniqueness and Applications
24
Wed
5:00 pm
Hogan Room
TBA
TBA
31
Wed
5:00 pm
Hogan Room
Felice Balarin
STARS (STatic Analysis of Reactive Systems)
*
February
7
Wed
5:00 pm
Hogan Room
Patrick Groeneveld
Engineering a Physical Synthesis System
8
Thu
5:00 pm
299 Cory
Carl Sechen
High Speed Digital Circuit Design Using Output Prediction Logic
*
14
Wed
5:00 pm
Hogan Room
Michael Kishinevsky
Synthesis of asynchronous circuits with relative timing assumptions
*
20
Tue
10:00 am
Hughes Room
Albert Benveniste
Distributed Hidden Markov Models (HMM)
*
21
Wed
5:00 pm
Hogan Room
Distributed code generation, desynchronisation, architecture generation, for dataflow synchronous languages: summary of results
*
28
Wed
5:00 pm
Hogan Room
Jin Yang
Generalized Symbolic Trajectory Evaluation
*
March
1
Thu
5:00 pm
Wang Room
Rob A. Rutenbar
Synthesis for Industrial-Scale Analog Intellectual Property
7
Wed
5:00 pm
Hogan Room
Michael Meyer
Micronetworks for SOC Integration
8
Thu
5:00 pm
Wang Room
Chung-Kuan Cheng
Research on Floorplanning
14
Wed
5:00 pm
Hogan Room
Amit Narayan
Design Closure of Very Deep Submicron ASICs
15
Thu
5:00 pm
TBA
Dr Lei. He
Modeling and Design of RLC Interconnects
21
Wed
5:00 pm
Hogan Room
Kenneth Shepard
Extraction and measurement of high-speed on-chip interconnect
28
Wed
5:00 pm
Hogan Room
Spring Recess
No Seminar
April
4
Wed
5:00 pm
Hogan Room
TBA
TBA
11
Wed
5:00 pm
Hogan Room
Shaz Qadeer
Predicate abstraction for software verification
*
18
Wed
5:00 pm
Hogan Room
Rajeev Murgai
Layout-Driven Logic Optimization
25
Wed
5:00 pm
Hogan Room
Tom Spyrou
Improving Team Productivity for RTL Designers
May
2
Wed
5:00 pm
Hogan Room
Peter Beerel
TBA
*
: Slides Available.
Comments and questions can be addressed to the
organizers
.
Back to
CAD Seminar Page
Back to
CAD Group Home Page