Fall 1997 CAD Seminar Schedule

  • Click on the speaker's name for a brief biography and contact information
  • Click on the title for a abstract of the talk. If we have electronic copies of transparencies or relevant papers,
    they can be found here, along with the abstract.
  • Please send comments and suggestions to the CAD seminar organizers.

    Month Date Day Time Venue Speaker Title
    August 27 Wed 5:00 pm Hogan Room F. Somenzi Minimizing BDDs
    September 3 Wed 5:00 pm Hogan Room M. Iyer Sequential Redundancy Identification
    4 Thu 2:00 pm Hogan Room M. Potkonjak Intellectual Property Protection =
    Constraints + Watermarking +
    10 Wed 5:00 pm Hogan Room H. Murata Rectangle Packing Based Placement
    17 Wed 5:00 pm Hogan Room R. Camposano Managing Complexity and Technology
    in EDA Tools
    24 Wed 5:00 pm Hogan Room K. McMillan A Compositional rule for Hardware
    Design Refinement
    October 1 Wed 5:00 pm Hogan Room R. McGeer The V++ Hardware Design Language
    8 Wed 10:30am Hogan Room S. Baranov The SYNTHESIS1 System for FSM Synthesis
    8 Wed 5:00 pm Hogan Room R. P. Kurshan Commercial Verification:
    10/97 (a status report)
    15 Wed 5:00 pm Hogan Room E. McCluskey Review of current research at Stanford
    University's Center for Reliable
    22 Wed 5:00 pm Hogan Room M. R. Mercer The Beginning of the End for Stuck-at-Fault
    Based Testing
    29 Wed 5:00 pm Hogan Room S. Reddy Properties of Faults in Synchronous
    Sequential Circuits and their Application to
    Test Generation, Logic Optimization and
    Testable Designs
    November 5 Wed 2:00 pm Wang Room E. Cerny An interface-oriented H/W specification
    and verification method
    5 Wed 5:00 pm Hogan Room M. Lefebvre The Emergence of Physical Synthesis
    as a Mainstream Design Technology
    6 Thur 5:00 pm Wang Room M. Kishinevsky Coupling asynchrony and interrupts:
    Place Chart Nets and their synthesis
    6 Thur 11:00 am Hogan Room Hiroaki Iwashita Forward model checking techniques
    oriented to buggy designs
    6 Thur 11:40 am Hogan Room T. Nakata Formal Verification of a
    System-on-a-Chip using BINGO
    7 Fri 1:30 pm Hogan Room B. Becker Decision Diagrams: Where do we go?
    7 Fri 5:00 pm Hughes Room S. Sapatnekar Fast Algorithms for Retiming large
    Digital Circuits
    14 Fri 1:30 pm Hogan Room C. Pixley Logic and Functional Verification at Motorola
    14 Fri 5:00 pm Hughes Room G. Cabodi
    S. Quer
    Advancements in Reachability Analysis
    using Transition Relations
    17 Mon 5:00 pm Hogan Room J. Jess Code Scheduling for Media Hardware Platforms
    18 Tue 5:00 pm Hogan Room W. Kunz Structural FSM Traversal - Theory and a Practical
    19 Wed 2:00 pm 293 Cory A. Pnueli Verifying Out-of-Order Executions
    19 Wed 5:00 pm Hogan Room C. Sechen Dynamic Logic Synthesis
    21 Fri 3:30 pm Wang Room J. Cong VLSI Interconnect Layout
    Optimization In Deep Submicron Designs
    26 Wed - - - Thanksgiving Break - No Seminar
    December 3 Wed 5:00 pm Hogan Room K. Olukotun Determining the Performance, Cost and
    Correctness of Processor-Based Systems
    5 Fri 3:30 pm Wang Room V. Tiwari Low-power High-performance Microprocessor
    10 Wed 5:00 pm Hogan Room D. Dill Symbolic verification of the Torch instruction
    fetch unit: A reality check
    11 Thu 2:00 pm Hughes Room S. Minato Exploiting All Simple Disjunctive
    Decompositions of Boolean Functions
    Based on Algebraic Factorization

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