Schedule Spring '97

5/22/97 (Thursday), 2pm 531 Cory: Gitanjali Swamy, Mentor Graphics. gms@eecs.berkeley.edu

"Incremental Methods for Logic-CAD" Abstract

5/13/97 (Tuesday), 2pm 531 Cory: Atsushi Sakurai, Fujitsu. sakurai@ed.fujitsu.co.jp

"The MMA and Its Design Technology" Abstract

5/12/97 (Monday), 4pm 405 Soda: Ugo Montanari, University of Pisa. ugo@csl.sri.com

"History-Dependent Automata" Abstract

5/7/97, 5pm 531 Cory: Sujit Dey, NEC. dey@ccrl.nj.nec.com

"High Level Power Optimization and Analysis Techniques" Abstract

5/5/97, 3pm 531 Cory: Shmuel Katz, SRI (on leave from Technion). katz@csl.sri.com

"Using Partial Orders to Verify Concurrent Systems" Abstract

5/2/97 (Friday), 11am 531 Cory: Soha Hassoun, University of Washington. soha@cs.washington.edu

"Architectural Retiming: A Technique for Pipelining Latency-Constrained Circuits" Abstract

4/30/97, 5pm 531 Cory: Steve Trimberger, Xilinx. steve.trimberger@xilinx.com

"A Time-Multiplexed FPGA" Abstract

4/23/97, 5pm 531 Cory: Lou Scheffer, Cadence. lou@Cadence.COM

"Understanding the issues beyond basic synthesis, placement and routing" Abstract

4/16/97, 5pm 531 Cory: Rajeev Murgai, Fujitsu Laboratories of America. murgai@fla.fujitsu.com

"Speeding Up Technology-Independent Timing Optimization by Network Partitioning" Abstract

4/9/97, 5pm 531 Cory: Debbie Marr, Intel Corp. dmarr@ichips.intel.com

"Multiprocessor Validation of the Pentium(R) Pro Processor" Abstract

4/2/97, 5pm 531 Cory: Hamid Savoj, Cadence. hamid@cadence.com

"Improvements in Technology Independent Optimization of Logic Circuits" Abstract

3/26/97 No Seminar (Spring Break)

3/19/97, 5pm 531 Cory: Tom Shiple, Synopsys. shiple@synopsys.com

"Analysis of Combinational Cycles in Synchronous Circuits" Abstract

3/12/97, 5pm 531 Cory: Peter Beerel, University of Southern California. pabeerel@eiger.usc.edu Ken Yun, University of California, San Diego. kyy@paradise.ucsd.edu

"The Design and Verification of a High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver" Abstract

3/5/97, 5pm 531 Cory: Jason Cong, University of California, Los Angeles. cong@cs.ucla.edu

"FPGA Mapping, Retiming, and Pipelining for Performance Optimization" Abstract

2/26/97, 5pm 531 Cory: Howard Wong-Toi, Cadence Berkeley Labs. howard@cadence.com

"Synthesizing Controllers for Linear Hybrid Automata" Abstract

2/19/97, 5pm 531 Cory: David Dill, Stanford University. dill@cs.stanford.edu

"Validity Checking for Combinations of Theories with Equality" Abstract

2/12/97, 5pm 531 Cory: Massoud Pedram, University of Southern California. massoud@zugros.usc.edu

"Power Estimation and Optimization in IC Design" Abstract

2/7/97 (Friday), 11am 531 Cory: Andreas Kuehlmann, IBM. kuehl@watson.ibm.com

"Equivalence Checking in Practice" Abstract

2/5/97, 5pm 531 Cory: Pinaki Mazumder, University of Michigan. mazum@eecs.umich.edu

"Parallel Algorithms for Multi-layer Wire Routing Problems" Abstract

1/29/97, 5pm 531 Cory: Ching-Tsun Chou, Fujitsu Labs of America. ctchou@fla.fujitsu.com

"Synchronous Verilog" Abstract

1/22/97, 10:30am 531 Cory: David LaPotin, IBM. dpl@austin.ibm.com

"Research Activities at the IBM Austin Research Laboratory" Abstract

1/22/97, 11am 531 Cory: Anirudh Devgan, IBM. devgan@austin.ibm.com

"Transistor-level Timing Simulation and Analysis" Abstract

1/22/97, 5pm 531 Cory: Sani Nassif, IBM. nassif@austin.ibm.com

"Manufacturability Analysis and Optimization" Abstract

1/15/97, 5pm 531 Cory: Leon Stok, IBM. stokl@watson.ibm.com

"Retiming Reviewed" Abstract